Effects of fluorine incorporation into HfO2 gate dielectrics on InP and In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors

Chen, Yen‐Ting; Han, Zhewen; Wang, Yanzhen; Xue, Fei; Zhou, Fei; Lee, Jack C.

doi:10.1063/1.3457388

Cited by 24 publications

(15 citation statements)

References 15 publications

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“…This is likely caused by In-rich IL formation and may explain the recently reported charge instability of InP/ HfO 2 interfaces. 21 In conclusion, we found that ALD Al 2 O 3 provides a high CB offset, of 2.7 eV, with ͑100͒InP. However, it is also observed that the formation of an IL due to oxidation of semiconductor may reduce the barrier height for electrons significantly, particularly if a high electric field is applied ͓cf.…”

mentioning

confidence: 84%

Electron band alignment between (100)InP and atomic-layer deposited Al2O3

Chou

Afanasʼev

Stesmans

et al. 2010

Applied Physics Letters

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mentioning

confidence: 84%

Electron band alignment between (100)InP and atomic-layer deposited Al2O3

Chou

Afanasʼev

Stesmans

et al. 2010

Applied Physics Letters

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“…[1][2][3][4][5] When InGaAs is used, it is grown on an indium phosphide (InP) buffer layer which itself is grown selectively in trenches patterned by a shallow trench isolation process on Si wafers. 6 This InP buffer layer needs to be planarized to remove the overburden and to smoothen the surface.…”

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confidence: 99%

Chemical Mechanical Polishing of InP

Peddeti

Ong

Leunissen

et al. 2012

ECS J. Solid State Sci. Technol.

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Results of a detailed study of different parameters of the polishing process and their influence on the removal rates (RRs) of InP are presented. RRs with silica-based slurries as well as generation of PH 3 were much higher in the acidic pH regions compared to those in basic pH regions. RRs were also higher than those obtained with harder alumina particles. Smaller silica particles led to higher RRs than larger particles at the same wt% loading, presumably due to the higher total particle surface area. These characteristics suggest an affinity between silica particles and InP similar to that observed earlier between Ta and silica. However, unlike with Ta, replacing the surface silanol groups of the silica particles with dimethyl silane did not suppress the RRs completely. It is proposed that InP removal by silica abrasives is facilitated by the formation of -Si-O-In-, -Si-In-and -Si-P-structures due not only to the reactivity of the silanol groups but also due to the combined effect of the electronegativity of Si atoms, the presence of lone pairs of electrons on In atoms on the InP surface and the electronegativity difference between Si and P.

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“…25 Fluorine incorporation into HfO 2 /InP and HfO 2 /In 0.53 Ga 0.47 As gate stacks was reported to improve the drain current and the transconductance and these improvements were attributed to a reduction in the fixed charge and the interface trap density. 26 Passivation of HfO 2 /InP gate stacks by an intermediate Al 2 O 3 layer was observed to enhance the drain current 2.5 times and the transconductance 4 times while reducing the interface trap density. 27 Fluorine treatment of InP/Al 2 O 3 /HfO 2 /TaN gate stacks was found to increase the drain current 100%, the transconductance 50%, and the channel mobility 56%; this enhancement was attributed to a reduction in the gate stack charge.…”

Section: Drain Current Versus Drain Voltage Characteristicmentioning

confidence: 97%

Closed-Form Model for High-k MOSFET Channel Parameters: Reflecting Non-Saturating Inversion Surface Potential, Gate Stack Traps, and Work Function Anomaly

Kar

2012

ECS J. Solid State Sci. Technol.

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Closed-form, textbook-appropriate equations have been derived for the drain current I D , the channel conductance g D , and the transconductance g m of high-k MOSFETs, incorporating high-k gate stack charges Q di,gsc , non-saturating inversion surface potential increase ϕ s,inv , and work-function difference φ MS . These ab initio relations, developed without imposing any assumptions, provide a clear view of the degrading effects of the high-k gate stack charges, the non-saturating inversion surface potential, and the semiconductor-metal work function difference on I D , g D , and g m . Rational estimates have been made of the latter which illustrate the relative weights of each of the three non-ideal factors in the degradation of the channel parameters of the high-k gate stack. The degradation appears to be most severe for the channel conductance, followed by the drain current, and then the trans-conductance. The work-function anomaly does not directly affect the trans-conductance for which the major degrading factor is the non-saturating surface potential. Even for moderate drain voltages, the numerical estimates reveal the drain current versus the drain voltage relation to become more non-linear in the case of the high-k gate stack. Comparison with the available experimental high-k gate stack data supports the import of these equations.The classical closed-form drain current versus the drain voltage relations for the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) were derived under the following assumptions: 1-3 1) No fixed or trap charges inside the bulk of the gate stack; 2) no interface traps or fixed charges at the semiconductor-dielectric interface; 3) saturation of the inversion surface potential to its value at the onset of strong inversion (ϕ s,inv,th ) for the entire strong inversion regime; 4) no semiconductor-metal work function difference. None of the above assumptions is tenable in the case of MOSFETs with high-k gate stacks, which are beset with enormous bulk charges and traps and work-function anomaly. 4,5 After strong inversion sets in, the surface potential far from saturating has been observed to keep increasing continuously over the entire strong inversion regime. 6,7 Hence the above assumptions taken together represent a serious contradiction to the reality that obtains in the case of the current high-k gate stacks.Numerical models have been developed to make more realistic estimates of the drain current and the related parameters of MOSFETs. However, closed-form, text-book type equations, derived from the first principles, are needed to provide a sound physical insight into the critical parameters. Needed are mathematical relations in closed form for the drain current I D , the channel conductance g D , and the transconductance g m which transparently illustrate how much the high-k gate stack charges, the non-saturating inversion surface potential, and the work function anomaly degrade the channel parameters. Even the recent semiconductor device and gate stack reference books s...

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Effects of fluorine incorporation into HfO2 gate dielectrics on InP and In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors

Cited by 24 publications

References 15 publications

Electron band alignment between (100)InP and atomic-layer deposited Al2O3

Electron band alignment between (100)InP and atomic-layer deposited Al2O3

Chemical Mechanical Polishing of InP

Closed-Form Model for High-k MOSFET Channel Parameters: Reflecting Non-Saturating Inversion Surface Potential, Gate Stack Traps, and Work Function Anomaly

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