Effects of electrical stressing in power VDMOSFETs

Stojadinović, N.; Manić, I.; Davidović, V.; Danković, Danijel; Djorić-Veljković, S.; Golubović, S.; Dimitrijev, Sima

doi:10.1016/j.microrel.2004.09.002

Cited by 21 publications

(19 citation statements)

References 24 publications

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“…This strictly decreasing variation in threshold voltage following a negative stress is different from that obtained by Ristić et al (2005), Stojadinovic et al (2005) and Stojadinović et al (2003). In fact, oxide trapped charges and interface traps created by the applied electrical stress govern the variation of the threshold voltage.…”

Section: Resultscontrasting

confidence: 66%

Comparison between positive and negative bias stress on N‐channel VDMOSFET transistors

Abboud

Habch

Cuminal

et al. 2013

International Journal of Structural Integrity

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If you would like to write for this, or any other Emerald publication, then please use our Emerald for Authors service information about how to choose which publication to write for and submission guidelines are available for all. Please visit www.emeraldinsight.com/authors for more information. About Emerald www.emeraldinsight.comEmerald is a global publisher linking research and practice to the benefit of society. The company manages a portfolio of more than 290 journals and over 2,350 books and book series volumes, as well as providing an extensive range of online products and additional customer resources and services.Emerald is both COUNTER 4 and TRANSFER compliant. The organization is a partner of the Committee on Publication Ethics (COPE) and also works with Portico and the LOCKSS initiative for digital archive preservation. AbstractPurpose -The purpose of this paper is to apply a negative gate bias stress in order to study instabilities of threshold voltage in N-channel power vertical double-diffused metal-oxide-semiconductor field effect transistor (VDMOSFET). Variations in gate oxide trapped charge and interface trap densities are also calculated. Design/methodology/approach -A threshold voltage shift is detected; the oxide and interface trap densities were evaluated based on a direct measurement of the gate to source capacitance and conductance. Findings -Results presented show that the threshold voltage is decreasing with stress time, the capacitance and conductance curves are altered by applied stress, also the oxide traps and the interface traps densities are increasing with stress time. Originality/value -The positive bias stress seems to be more destructive in the case of the studied devices.

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Section: Resultscontrasting

confidence: 66%

Comparison between positive and negative bias stress on N‐channel VDMOSFET transistors

Abboud

Habch

Cuminal

et al. 2013

International Journal of Structural Integrity

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“…During NBT stresses V T of investigated p-channel power VDMOSFETs was more significant in the cases of higher stress voltage and/or temperatures [25]. The underlying phenomenon leading to the observed V T in the stressed devices is the stress-induced buildup of N ot and N it .…”

Section: Nbt Stress Effectsmentioning

confidence: 93%

“…Note that more significant negative V T is obtained at higher temperatures and/or higher gate voltages, i.e. higher oxide electric fields [24][25][26][27][28].…”

Section: Development Of Advanced Electronic Industry Is Based On Combmentioning

confidence: 99%

“…NBT stress-induced threshold voltage instabilities in commercial power VDMOSFETs, as well as the implications of related degradation on device lifetime have been extensively investigated in our research in the last decade [27,[42][43][44]. Although in many experiments devices have been subjected to various NBT stress (static or pulsed) and annealing conditions [9,23,25,45,46,[48][49][50][51][52], in this section a part of results obtained during static NBT stress and annealing is presented, with attention to insight into the NBTI as a result of sequential NBT stress and bias annealing steps.…”

Section: Nbt Stress Effectsmentioning

confidence: 99%

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NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs

et al. 2018

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In this paper we provide an overview of instabilities observed in commercial power VDMOSFETs subjected to irradiation, NBT stress, and to consecutive exposure to them. The results have indicated that irradiation of previously NBT stressed devices leads to additional threshold voltage shift, while NBT stress effects in previously irradiated devices depend on the gate bias applied during irradiation and on the total dose received. This points to the importance of the order of applied stresses, indicating that for proper insight into the prediction of device behaviour not only harsh conditions, but also the order of exposure have to be considered. It has also been shown that changes in the densities of oxide trapped charge and interface traps during spontaneous recovery after each of applied stresses can be significant, thus leading to additional instability, even though the threshold voltage seems to remain stable, pointing to the need for clarifying the responsible mechanisms.

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“…Threshold voltage is widely accepted as a well-suited parameter that can be used as a degradation monitor for the lifetime estimation. In order to estimate the lifetime of investigated VDMOSFETs the following dependence of ∆V T on the stress field (E), time (t), and temperature (T ) during the static NBT stress has earlier been derived: [34,42,43] ∆V T = AE m t n exp(−E a /kT ),…”

Section: Duty Cycle Dependencementioning

confidence: 99%

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET

Danković¹,

Stojadinović²,

Prijić³

et al. 2015

Chinese Phys. B

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In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal–oxide semiconductor field-effect transistors (VDMOSFETs) subjected to negative bias temperature (NBT) stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps (permanent component). Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.

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Effects of electrical stressing in power VDMOSFETs

Cited by 21 publications

References 24 publications

Comparison between positive and negative bias stress on N‐channel VDMOSFET transistors

Comparison between positive and negative bias stress on N‐channel VDMOSFET transistors

NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET

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