Effects of active layer thickness on performance and stability of dual-active-layer amorphous InGaZnO thin-film transistors

Abstract

Dual-active-layer (DAL) amorphous InGaZnO (IGZO) thin-film transistors (TFTs) are fabricated at low temperature without post-annealing. A bottom low-resistance (low-R) IGZO layer and a top high-resistance (high-R) IGZO layer constitute the DAL homojunction with smooth and high-quality interface by in situ modulation of oxygen composition. The performance of the DAL TFT is significantly improved when compared to that of a single-active-layer TFT. A detailed investigation was carried out regarding the effects of the thickness of both layers on the electrical properties and gate bias stress stabilities. It is found that the low-R layer improves the mobility, ON/OFF ratio, threshold voltage and hysteresis voltage by passivating the defects and providing a smooth interface. The high-R IGZO layer has a great impact on the hysteresis, which changes from clockwise to counterclockwise. The best TFT shows a mobility of 5.41 cm 2 /V•s, a subthreshold swing of 95.0 mV/dec, an ON/OFF ratio of 6.70 × 10 7 , a threshold voltage of 0.24 V, and a hysteresis voltage of 0.13 V. The value of threshold voltage shifts under positive gate bias stress decreases when increasing the thickness of both layers.

Dual-active-layer InGaZnO high-voltage thin-film transistors

“…First, Cr gate layer is deposited on fused quartz substrate by radio frequency (RF) magnetron sputtering, and then patterned by UV-lithography and wet etching. A 100 nm thick Al 2 O 3 gate dielectric layer is deposited by atomic layer deposition at 200 • C. The Low-R (∼13.5 nm) and High-R IGZO (∼18.9 nm) layers are sequentially deposited by RF-magnetron sputtering at 100 • C with different Ar/O 2 ratios, which have been optimized in our previous study [20]. Then the DAL IGZO channel and Al 2 O 3 are patterned by UV-lithography and wet etching.…”

“…Dual-active-layer (DAL) structure has been adopted to achieve high-performance TFTs [19,20]. The defects in the channel and the interface between the channel and dielectric can be efficiently passivated by a low-resistance (Low-R) layer with high electron concentration, while a high-resistance (High-R) layer can be used to achieve a desirable threshold voltage.…”

Improvement of properties of top-gate IGZO TFT by oxygen-rich ultrathin in situ ITO active layer

“…9) Up to now, a few techniques have been used to reduce the hysteresis of TFT devices, including composite insulating layer, 9) stacked insulating layer, 7,10) surface treatment of the active layer, 11) and dual-active-layer. [12][13][14][15] A dual-active-layer based on in situ deposition and synchronous patterning has been demonstrated to effectively reduce trap density at the dielectrics/ active interface and improve the stability of the bottom gate TFT, such as low/high-resistance IGZO, 13,16,17) In-Sn-O (ITO)/IGZO 18,19) and ITO/Ti-Zn-O. 20) However, there are few further studies on the mechanism of hysteresis and negative bias illumination stability (NBIS).…”

“…24) The high-valence Sn 4+ and excess oxygen in ultrathin oxygenrich ITO play the roles of providing abundant free electrons and repairing interfacial defects, respectively. 13,20,25) As shown in the insert of Fig. 2(a), the green squares show the magnified area of the forward-backward sweep transfer curves, and the gate voltage changes from −20V to 20 V back to −20V.…”

“…27) The oxygen-rich ultrathin ITO channel can provide additional electrons to remedy the trapped electrons in the insulating layer and provide a large amount of electrons to passivate interface defects, thereby reducing ΔV H . 13) In addition, the high ΔV H may also be ascribed to the involvement of the border traps. 26) So the defect state of the insulating/channel interface is passivated with oxygen-rich ultrathin ITO, so that the electrons cannot be bound by the interface defect, thereby reducing the ΔV H .…”