Effectiveness of trace sampling for performance debugging tools

Martonosi, Margaret; Gupta, Anoop; Anderson, Thomas E.

doi:10.1145/166962.167023

Cited by 8 publications

(9 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A means to solve this problem is to limit the object of measurement. Effectiveness of Trace Sampling for Performance Debugging Tools [13] is a tracer in which the amount of data is reduced by focusing on memory access. In this system, memory accesses in the program that is the object of measurement are sampled, and the overall memory access performance is estimated by performing a simulation based on the obtained data.…”

Section: Related Studiesmentioning

confidence: 99%

Development of instruction tracer for performance evaluation

Morimoto

Komiyama

Mouri

et al. 2004

Electron Comm Jpn Pt III

View full text Add to dashboard Cite

SUMMARYApplications such as network server programs and distributed multimedia applications, in which system calls and input/output processing are frequently used, are highly dependent on the operating system. In evaluating the performance of such applications, the execution data for the application and the operating system must be acquired consistently. Conventionally, the performance of a program has mostly been examined through the occurrences of particular events, by means of the performance monitoring function provided by the CPU. The most frequent is the measurement of time based on the cumulative number of clocks in the CPU. In the present computer environment, these values vary depending on the measurement timing. In addition, in these methods, the information concerning the time of occurrence is not preserved when multiple events occur, and there is no means of analyzing the dependency among the events. It is thus difficult for the user to locate the reason for the variation of the value. In order to solve these problems, this paper considers memory access as the measure for performance evaluation. The "TSURU" kernel level instruction tracer, the set of "TSURU tools" that analyze the output data from TSURU, and the "TSURU library" used to construct TSURU tools, are proposed. TSURU can acquire dynamic information such as the execution instruction sequence, the refer address, and the interrupt. Using the TSURU tools to analyze the data acquired by TSURU, the operation of the program under consideration can be traced, and the execution time and the page fault generation rate can be determined. Based on this result, the factors responsible for performance degradation can be analyzed, and the performance improvement obtainable by solving the problem can be estimated. With the TSURU library, the user can easily construct TSURU tools.

show abstract

Section: Related Studiesmentioning

confidence: 99%

Development of instruction tracer for performance evaluation

Morimoto

Komiyama

Mouri

et al. 2004

Electron Comm Jpn Pt III

View full text Add to dashboard Cite

show abstract

“…Trace sampling was also mentioned as another and more sophisticated technique for reducing the trace size [14]. Instead of picking a trace of T consecutive references, the trace is split into a number of randomly located intervals within a larger trace.…”

Section: Speedup and Accuracymentioning

confidence: 99%

“…Several studies have demonstrated that sampling methods can bring significant speedups without loosing much accuracy [14,17,16]. However, they do not propose a simple and comprehensive method to control the associated accuracy issues; indeed, the accuracy decreases relatively quickly with the speedup since the principle is again to reduce the trace size in order to decrease simulation time.…”

Section: Introductionmentioning

confidence: 99%

DiST

Girbal

Mouchard

Cohen

et al. 2003

Proceedings of the 2003 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems

View full text Add to dashboard Cite

While architecture simulation is often treated as a methodology issue, it is at the core of most processor architecture research works, and simulation speed is often the bottleneck of the typical trialand-error research process. To speedup simulation during this research process and get trends faster, researchers usually reduce the trace size. More sophisticated techniques like trace sampling or distributed simulation are scarcely used because they are considered unreliable and complex due to their impact on accuracy and the associated warm-up issues.In this article, we present DiST, a practical distributed simulation scheme where, unlike in other simulation techniques that trade accuracy for speed, the user is relieved from most accuracy issues thanks to an automatic and dynamic mechanism for adjusting the warm-up interval size. Moreover, the mechanism is designed so as to always privilege accuracy over speedup. The speedup scales with the amount of available computing resources, bringing an average 7.35 speedup on 10 machines with an average IPC error of 1.81% and a maximum IPC error of 5.06%.Besides proposing a solution to the warm-up issues in distributed simulation, we experimentally show that our technique is significantly more accurate than trace size reduction or trace sampling for identical speedups. We also show that not only the error always remains small for IPC and other metrics, but that a researcher can reliably base research decisions on DiST simulation results. Finally, we explain how the DiST tool is designed to be easily pluggable into existing architecture simulators with very few modifications.

show abstract

“…After experimenting with various sample sizes and sampling ratios, we settled on a sample size of 500,000 references and a sampling ratio of 0.1. The process of tuning these parameters for a given workload is important [9,5]. The rationale for our choice for these Windows NT desktop application traces is briefly discussed in Appendix A.…”

Section: Sampling Techniquesmentioning

confidence: 99%

“…These demands can be greatly reduced by employing sampling techniques at the expense of providing only a statistical estimate of the properties of a full trace. Previous studies [9,6,5] contain results for other workloads and caches and discuss the conditions under which sampling may, or may not, be used.…”

Section: Introductionmentioning

confidence: 99%