Effective support of simulation in computer architecture instruction

Abstract

Abstract

Integrating Formal Verification into an Advanced Computer Architecture Course

“…Traditionally, the principles of pipelined and superscalar execution have been taught by using trace-driven simulation [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][71][72][73][74] , or FPGA-based hardware emulation 21,[30][31][32][33][34] . Surveys of simulation resources are presented by Wolffe et al 75,77 , and Yehezkel et al 76 However, simulator bugs and modeling inaccuracies can lead to significant errors in performance measurements [78][79][80][81][82][83][84] , and so may result in wrong design decisions.…”

“…Surveys of simulation resources are presented by Wolffe et al 75,77 , and Yehezkel et al 76 However, simulator bugs and modeling inaccuracies can lead to significant errors in performance measurements [78][79][80][81][82][83][84] , and so may result in wrong design decisions. To avoid bugs, Weaver et al 16 extended their tracedriven simulator with a dynamic checker, which is similar to the checker processor in the DIVA architecture 85 , and is used to compare the superscalar simulator results with those produced by a non-pipelined simulator. While such checker can detect bugs triggered by the benchmarks simulated so far, it does not guarantee full correctness, so that bugs may still remain-to be activated by other benchmarks-and affect the performance measurements; it does not identify modeling inaccuracies that lead to imprecise performance measurements; and does not solve the problem of how to prove the correctness of pipelined processors for all execution sequences.…”

“…Traditionally, the principles of pipelined and superscalar execution have been taught with three approaches: 1) trace-driven simulation with existing tools [6][7][8][9][10][11][12][13][14][15][16][17][18] ; or 2) implementation of a trace-driven simulator by using a programming language such as C, often by filling only missing sections in skeleton code provided by the instructors [19][20][21] ; or 3) implementation of a processor using a commercial hardware description language (HDL), such as Verilog 22 or VHDL [23][24] as reported by several authors [25][26][27][28] , or an academic HDL 20,29 , and then simulating it with existing tools or with an FPGA-based hardware emulation system 21,[30][31][32][33][34] . In the second and third approaches, the implementations are verified with test sequences provided by the instructors, and possibly with additional test sequences defined by students.…”

“…Symbolic Trajectory Evaluation also required extensive manual work to prove the correctness of just a register-immediate OR instruction in a bit-level 5-stage ARM processor 135 . Other researchers had to limit the data values to 4 bits, the register file to 1 register, and the ISA to 16 . Custom-tailored, manually defined rewriting rules were used to formally verify a 5-stage DLX 142,143 , and similar 4-stage processors [144][145][146][147] , but would require modifications to work on designs described in different coding style, and significant extensions to scale for dual-issue superscalar processors.…”

Teaching computer architecture using an architecture description language

“…SimpleScalar offers a MIPS like ISA, called PISA, for didactical purposes, along with a GCC port to this target. MASE [10] is a graphical simulation environment built on top of SimpleScalar. RaVi [8] comprises a set of multimedia MIPS basedmodules for dynamic visualization of hardware behavior.…”