Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test

Almeida, Fabiana Damasceno; Bernardi, P.; Calabrese, D.; Restifo, Marco; Reorda, M. Sonza; Appello, D.; Pollaccia, G.; Tancorre, V.; Ugioli, R.; Zoppi, G.

doi:10.1109/ddecs.2019.8724644

Cited by 13 publications

(6 citation statements)

References 14 publications

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“…The MCU is the most significant component of the tester architecture, and it works under the control of a host PC, which sends high-level commands and reads back the final results of the stress operations. A host PC may drive more than a single microcontroller board, thus allowing to achieve a sufficiently high level of test parallelism [10]. The proposed tester architecture can sequence bits to the pins of the DUT.…”

Section: Multicore Tester Architecturementioning

confidence: 99%

“…Furthermore, it allows for storing multiple stress patterns, ranging from selective full scan ATPG patterns to LBIST-oriented patterns. This allows providing complete stress able to exacerbate potential latent defects before the final tests, e.g., System Level Test [10].…”

mentioning

confidence: 99%

“…This approach looks in the imperative direction of test equipment optimization. The proposed methodology allows performing the Burn-In oriented internal stress procedure in other test steps, such as applying it along with the System Level Test phase [10]. The MCU-based tester stimulates scan ports as BI testers do with specialized architectures [11] [12],.…”

mentioning

confidence: 99%

“…Nevertheless, it raises new issues, such as the availability of large channel memories typical of pure Burn-In equipment. As described in [10], the sustainability of the approach is directly related to the MCU cost and their re-usability for different DUTs. Cheap architectures are preferable, but they do not provide enough storage resources; therefore, a major challenge stands in reducing memory demands.…”

mentioning

confidence: 99%

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A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress

Bernardi

Appello

Bertani

et al. 2023

IEEE Trans. Comput.

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Burn-In test equipment usually owns extensive memory capabilities to store pre-computed patterns to be applied to the circuit inputs as well as ad-hoc circuitries to drive and read the DUT pins during the BI phase. The solution proposed in this paper dramatically reduces the memory size requirement and just demands a generic microcontroller unit (MCU) equipped with a couple of embedded processors, some standard common peripheral units, and a few KB memories. Moreover, the proposed Burn-In tester could be integrated into a System Level Test equipment which is typically based on MCUs to communicate functionally with the DUT. This paper provides full details about the architecture of such a low-cost innovative tester, which can supply the DUT with unlimited pseudo-random patterns created autonomously by the MCU firmware from any selected seed. The tester prototype developed to collect experimental results includes a low-cost System-on-Chip based on a multi-core MCU and a set of peripheral cores, encompassing timers and Direct Memory Access modules. The tester prototype is used to stress an automotive chip accounting for about 20 million gates, 700 thousand scan flip-flops, and several scan modes. The combination of pseudo-random pattern generation with the ability to control different scan and Design for Testability (DfT) modes, including LBIST, permits to reach a higher coverage of stress metrics than by the application of a limited set of pre-computed ATPG patterns. The toggle coverage level reached is up to 95.89%. The application speed achieved by the tester with non-optimized connections is up to about 10MHz.

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Section: Multicore Tester Architecturementioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress

Bernardi

Appello

Bertani

et al. 2023

IEEE Trans. Comput.

Self Cite

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“…When considering application areas where Burn-In test is required (e.g., automotive), cost reduction can be achieved by combining Burn-In test and SLT. In this case, the tester infrastructure developed for Burn-In (characterized by high parallelism) can be adapted to account for SLT requirements as well [7].…”

Section: B Slt-induced Costs and Complexitiesmentioning

confidence: 99%

Exploring the Mysteries of System-Level Test

Polian,

Anders,

Becker

et al. 2021

Preprint

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System-level test, or SLT, is an increasingly important process step in today's integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We discuss the types or failures covered by SLT, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT. Observing that the theoretical understanding for all these questions has not yet reached the level of maturity of the more conventional structural and functional test methods, we outline new and promising directions for methodical developments leveraging on recent findings from software engineering.

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A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips

Angione,

Appello,

Bernardi

et al. 2023

IEEE Access

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Complexity and performance of Automotive System-on-Chips have exponentially grown in the last decade, also according to technology advancements. Unfortunately, this trend directly and profoundly impacts modern Electronic Design Automation tools, which must handle very large amounts of logic gates. The consequence is an exponential increase in computation times, potentially leading to significant production delays. In the context of Burn-In, to reduce the computing time, the stress specification is often relaxed due to the difficulty of grading extensive pattern sets, and it may result in the insurgence of unstressed circuit zones. As a matter of fact, current Electronic Design Automation software tools provide limited capabilities to effectively quantify stress effectiveness, investigate perpattern set coverage loss, and compute layout-aware stress metrics. This article proposes a toolchain to overcome the limitations mentioned above. We propose a complete software flow to evaluate Burn-In stress patterns through standard toggle coverage and activity effectively. Together with these standard metrics, this article illustrates how to complement traditional measurement with layout-aware toggle coverage metrics. By exploiting parallel programming paradigms and machine learning algorithms, the proposed toolchain drastically reduces computation time for evaluating traditional stress metrics, and it offers new analysis metrics to test engineers conceiving the Burn-in stress patterns. In addition, the toolchain offers some commodities to superimpose the generated stress from different patterns and visualize it over the SoC layout through a heatmap, providing great benefits to test engineers in charge of composing Burn-In recipes. We validated our toolchain on two industrial devices from STMicroelectronics belonging to the SPC58 and SPC56 families, which include around 20 million and 2.7 million gates, respectively.

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Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test

Cited by 13 publications

References 14 publications

A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress

A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress

Exploring the Mysteries of System-Level Test

A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips

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