Effective In-Vehicle Network Training Strategy for Automotive Engineers

Byun, Jin Young; Park, Jae Wan; Kim, Do Yeon; Jeon, Jae Wook

doi:10.1109/access.2022.3158269

Cited by 3 publications

(1 citation statement)

References 15 publications

(9 reference statements)

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“…Secondly, the low delay and low jitter characteristics ensure Quality of Service (QoS) for various types of messages. Recognized as the backbone of next-generation and future automotive E/E architectures, automotive Ethernet is poised to play a pivotal role in shaping the future of vehicular communication [5,13,14,62,[71][72][73][74][75].…”

Section: Automotive Ethernetmentioning

confidence: 99%

Review of Electrical and Electronic Architectures for Autonomous Vehicles: Topologies, Networking and Simulators

Wang,

Guo,

Cao

et al. 2024

Automot. Innov.

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With the rapid development of autonomous vehicles, more and more functions and computing requirements have led to the continuous centralization in the topology of electrical and electronic (E/E) architectures. While certain Tier1 suppliers, such as BOSCH, have previously proposed a serial roadmap for E/E architecture development, implemented since 2015 with significant contributions to the automotive industry, lingering misconceptions and queries persist in actual engineering processes. Notably, there are concerns regarding the perspective of zone-oriented E/E architectures, characterized by zonal concentration, as successors to domain-oriented E/E architectures, known for functional concentration. Addressing these misconceptions and queries, this study introduces a novel parallel roadmap for E/E architecture development, concurrently evaluating domain-oriented and zone-oriented schemes. Furthermore, the study explores hybrid E/E architectures, amalgamating features from both paradigms. To align with the evolution of E/E architectures, networking technologies must adapt correspondingly. The networking mechanisms pivotal in E/E architecture design are comprehensively discussed. Additionally, the study delves into modeling and verification tools pertinent to E/E architecture topologies. In conclusion, the paper outlines existing challenges and unresolved queries in this domain.

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