Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits

Chang, Yi‐Fan; Huang, Ruei-Yang; Jiang, Jie-Hong R.

doi:10.1109/async.2019.00011

Cited by 9 publications

(2 citation statements)

References 17 publications

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“…Therefore, NOT gate propagates the changes before the end of signals' alteration. The asynchronous circuits are gaining a lot of attention in recent years [32][33][34][35][36]. Since we have designed our proposed Majority-voter so that it can be used in the synchronous and asynchronous realization of digital circuits.…”

Section: Majority Tmr Votermentioning

confidence: 99%

Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme

Sheikhpur

Taheri

Ansari³

et al. 2021

IET Computers & Digital Tech

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Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low-cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the reliability of our AES architecture, the reliability of voter is very important, for which reason we have introduced a novel voting scheme include a majority voter (named TMR voter) and an error barrier element (named DMR voter). In this paper, a reliable and secure 32-bit data-path AES implementation based on our robust fault resilient approach is developed. We illustrate that the proposed architecture can tolerate up to triple-bit (byte) simultaneous faults at each pipeline stage's logic and verify our claim through extensive error simulations. Error simulation results also show that our architecture achieves close to 100% fault-masking capability for multiple-bit (byte) faults. Finally, it is shown that the Application-Specific Integrated Circuit implementation of the fault-tolerant architectures using the composite field-based S-box, CFB-AES, and ROMbased S-box, RB-AES allows better area usage, throughput and fault resilience trade-off compared to their counterparts. So, it provides the most appropriate features to be used in highly-secure resource-constraint applications.

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Section: Majority Tmr Votermentioning

confidence: 99%

Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme

Sheikhpur

Taheri

Ansari³

et al. 2021

IET Computers & Digital Tech

View full text Add to dashboard Cite

show abstract

“…The circular STP circuit was intended to be implemented on application specific integrated circuits (ASICs), whereas it is becoming widely preferable to utilize commercial fieldprogrammable gate array (FPGA) devices for achieving not only rapid and inexpensive prototyping and evaluation of a target cir-cuit but also the implementation of the final products of asynchronous circuits [2], [3]. Although such FPGA devices and their EDA tools are oriented toward implementing synchronous circuits, STP circuits whose style is categorized into so-called bundled-data structurally resemble synchronous circuits, with the exception that they transfer data by employing a so-called handshake protocol instead of using a global clock signal and several research efforts have exploited this similarity and made it easier to design the STP circuits on the FPGA devices by exercising the industry-standard EDA tools of FPGA.…”

Section: Introductionmentioning

confidence: 99%

EDA-oriented FPGA Circuit Design Method for Four-phase Bundled-data Circular Self-timed Pipeline

Sannomiya

Iwata

Sato

et al. 2023

Journal of Information Processing

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Self-timed pipelines (STPs) are becoming attractive because of their power performance efficiency. A circular STP which realizes a looped data flow is necessary to directly implement not only iterative or recursive operations but also circular data paths for program execution. To facilitate product development or prototyping of STP circuits on a commercial field-programmable gate array (FPGA), several research efforts have already made it possible to utilize industry-standard electronic design automation (EDA) tools. However, how to adequately achieve a circular STP whose data transfer is realized by a so-called four-phase bundled-data is still unknown. In this paper, we point out that conventional circuits lead to a design failure or even unacceptably deteriorated throughput because EDA tools improperly interpret their configuration, especially in the realization of functions such as pipeline branching and a data copy and erasure. We propose a circular STP design method composed of both a low-latency handshake circuit configuration and its design procedure. Our proposed method guides the EDA tools to exploit FPGA's intrinsic low-latency paths. We evaluate a circular STP implementing a data-driven processor under corner conditions and show that our method can extract the maximum throughput of target pipelined circuits, which indicates the circular STPs wider applicability.

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A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication

Oliveira

Duarte

Batista

2021

2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS)

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Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits

Cited by 9 publications

References 17 publications

Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme

Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme

EDA-oriented FPGA Circuit Design Method for Four-phase Bundled-data Circular Self-timed Pipeline

A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication

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