Effective BIST for crosstalk faults in interconnects

Rudnicki, T.; Gucwa, K.; Hlawiczka, A.

doi:10.1109/ddecs.2009.5012120

Cited by 7 publications

(14 citation statements)

References 23 publications

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“…Further considerations are provided for comparison between operation of the (2n-1)-SR-TPG circuit and the solution already disclosed in [28]. To generate test vectors required to stimulate crosstalk faults in an n-bit interconnection bus study [28] assumes application of a Linear Feedback Shift Register (LFSR) with the length of 2n bits (2n-LFSR).…”

Section: Comparison Between the (2n-1)-sr-tpg Circuit Andmentioning

confidence: 99%

“…To generate test vectors required to stimulate crosstalk faults in an n-bit interconnection bus study [28] assumes application of a Linear Feedback Shift Register (LFSR) with the length of 2n bits (2n-LFSR). Actually the 2n-LFSR is made up of a shift register with its length of 2n supplemented with an external linear feedback with only XOR gates.…”

Section: Comparison Between the (2n-1)-sr-tpg Circuit Andmentioning

confidence: 99%

“…Thus, it proves indispensable to consider crosstalk faults in manufacturing tests [1], [19], [28], [23]. To detect, classify and localize dynamic faults it is necessary to supply test vectors to the input of the interconnection network at the rates that correspond to the nominal frequency of the circuit operation, i.e.…”

Section: Introductionmentioning

confidence: 99%

“…Such a one-chip integrated circuit, referred to as System-on-Chip (SoC) is made up of a set of embedded cores that communicate with each other via a network of long dedicated connections implemented, for instance, as shared bus lines [23], [24], [28]. In parallel, the idea of data exchange between modules of the integrated circuit via a Network-on-Chip (NoC) has become pretty popular over the recent years [13], [33], [25], [10], [5], [20], [17], [8], [12].…”

Section: Introductionmentioning

confidence: 99%

“…It entails the need to apply various techniques for built-in self-testing of interconnections (IBIST) [4], [26], [32], [27], [23], [29]. Conventional IBIST architectures for bus-type interconnections comprise a Test Patter Generator (TPG) for stimulating input vectors and an analyzer of test responses [37], [14], [11], [15], [28], [23], [29].…”

Section: Introductionmentioning

confidence: 99%

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New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

Garbolino

2015

International Journal of Electronics and Telecommunications

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Abstract-The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built-in blocks within a System-on-Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of the previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitive nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence. This study is dedicated to an innovative structure of a test pattern generator aimed at stimulation of crosstalk faults that may happen to bus-type connections. The fully scalable and synthesizable model of such a TPG unit has been developed in the VHDL language. The model was subjected to thorough investigations with regard to the length of the output test sequence and the associated hardware overhead. KeywordsThe TPG disclosed in this study is an improved option of the solution already described in [9]. The new design of the TPG benefits from reduction in length of the shift register and alteration of the test vector counter. These measures made it possible to achieve a TPG structure that highlights with less hardware overhead and much higher operation frequency than the solution presented in [9].

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Section: Comparison Between the (2n-1)-sr-tpg Circuit Andmentioning

confidence: 99%

Section: Comparison Between the (2n-1)-sr-tpg Circuit Andmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

Garbolino

2015

International Journal of Electronics and Telecommunications

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Stress-Aware Periodic Test of Interconnects

2021

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Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.

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Detection of Crosstalk Faults in Field Programmable Gate Arrays (FPGA)

Das

Roy

Rahaman

2014

J. Inst. Eng. India Ser. B

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In this work, a Built-in-Self-Test (BIST) technique has been proposed to detect crosstalk faults in FPGA and run time congestion and to provide the crosstalk aware router for FPGA. The proposed BIST circuits require less overhead as compared to earlier techniques. The proposed detector can detect any logic hazard or delay due to crosstalk. A technique has also been proposed to avoid the crosstalk by routing the path in such a way that no interference occurs between the interconnects. The proposed router has achieved better utilization of routing resource to determine the net as compared to the earlier works. The proposed scheme is simulated in MATLAB and verified using Xilinx ISE tools and Modelsim 6.0. The router is implemented by using class provided by JBits for Xilinx, Vertex-II FPGA. It has been found that the results are quite encouraging.

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Effective BIST for crosstalk faults in interconnects

Cited by 7 publications

References 23 publications

New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

Stress-Aware Periodic Test of Interconnects

Detection of Crosstalk Faults in Field Programmable Gate Arrays (FPGA)

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