Effective analytical delay model for transistor sizing

Wo, Zhaojun; Koren, Israel

doi:10.1145/1120725.1120882

Cited by 1 publication

(5 citation statements)

References 16 publications

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“…And it is accurate enough to simulate the channel current for submicron technology such as 0.25um and 0.18um [15]. Because it is simple, it is widely used to induce kinds of analytical formula for delay simulation [6,14,15]. The following is the detail description…”

Section: Transistor-level Simulator 21 Modified Alpha-power Lawmentioning

confidence: 99%

“…With technology scaling into nanometer [1], power becomes as important as performance so that low-power design research are showing prosperous [2,3,4,5,6,7,8,9]. Although Rampant process variations impact influences on low power design [7,9], researchers persist on study about deterministic methods of low power design because deterministic methods are the bases of statistical ones [3,4].…”

Section: Introductionmentioning

confidence: 99%

“…Although Rampant process variations impact influences on low power design [7,9], researchers persist on study about deterministic methods of low power design because deterministic methods are the bases of statistical ones [3,4]. Thanks to the fine granularity, transistor-level low-power design methods can reduce more leakage power than gate-level counterparts [5,6]. It is far more important to develop the general transistor-level low-power design methodology for nanometer VLSI marked with high leakage power.…”

Section: Introductionmentioning

confidence: 99%

“…In gate-level optimization, transistor parameters such as channel width [2,3,4], length [8], threshold voltage (V T 0 ) [2,3,4] are simultaneous sized for all PMOS (or NMOS) transistors in a gate. For the benefit of more power reduction, few researchers try to optimize CMOS circuits on transistor level [5,6]. Because they employ LUT [5] or analytical [6] methods, they can simply size only one parameter such as V T 0 [5] or width [6] on transistor level.…”

Section: Introductionmentioning

confidence: 99%

“…For the benefit of more power reduction, few researchers try to optimize CMOS circuits on transistor level [5,6]. Because they employ LUT [5] or analytical [6] methods, they can simply size only one parameter such as V T 0 [5] or width [6] on transistor level.…”

Section: Introductionmentioning

confidence: 99%

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General transistor-level methodology on VLSI low-power design

Luo

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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In this work, we modify the Alpha-Power Law to accurately simulate BSIM3-70nm gate delay on transistor level. Combined with efficient power analysis methods, we develop one transistor-level simulator to efficient estimate performance and power for CMOS gates consisting of heterogeneous transistors. Furthermore, we propose a novel transistor-level optimization engine consisting of two-step algorithms. The former gate-space algorithm uses the clustering strategy to cut down algorithm complexity. The latter transistor-space algorithm employs fine granularity to pursue reducing more power consumption. Experiments show the following advantages: 1. Our transistor-level simulator takes average 1.0ms (on an ordinary PM1.4G-256M laptop computer) to analyze one gate and can accurately estimate circuit delay with only 2 − 7% worst-case error. 2. Our methodology is so general that it can analyze and optimize heterogeneous circuit in which each transistor may have its own different V T 0 , channel width and length. 3. In the transistor-level width+V T 0 +length-sized optimization, our engine takes feasible running time (856.4s for C7552) to cut down 22.58%(average) and 43.02%(maximum) leakage power caused by gate-level optimum solution nearly without penalty of active power.

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