Effect of Underfill Formulation on Large-Die, Flip-Chip Organic Package Reliability: A Systematic Study on Compositional and Assembly Process Variations

Paquet, M.-C.; Dufort, Catherine; Lombardi, T.; Sinha, Tuhin; Hasegawa, Masahiro; Okoshi, Kodai; Kohara, Kazuyuki

doi:10.1109/ectc.2016.21

Cited by 4 publications

(1 citation statement)

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“…Many of the reliability failures in flip-chip packages result from delaminations or cracks in the underfill material, which is applied between the die and the substrate to alleviate the effect of the aforementioned CTE mismatches on the solder joints [3]. Several types of underfill failure modes, such as the interface delamination and cracking, are observed in accelerated temperature cycling tests [4][5]. The cracks in the underfill may not initially cause an electrical failure, but may propagate over time into the solder joints and the die back end of line (BEOL), thus resulting in device failure [6].…”

Section: Introductionmentioning

confidence: 99%

Using Confocal Microscopy and Digital Image Correlation to Measure Local Strains Around a Chip Corner and a Crack Front

Yang

Souare

Sylvestre

2020

IEEE Trans. Device Mater. Relib.

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In a flip chip package, the chip corner areas which are embedded in the underfill material are often critical to the damage initiation, since a stress concentration usually exists at these locations. A high level of stress concentration often promotes crack initiation from the chip corner. In order to better understand the local deformation around chip corners and crack tips, a method based on laser scanning confocal microscopy combined with the digital image correlation (confocal-DIC) was developed to measure local strain directly in deformed, transparent objects. A transparent epoxy resin with alumina particle fillers was used in four different types of samples, which were fabricated for the purpose of validation. A non-constrained sample and a thin-layer sample were used to verify the isotropic thermal expansion and the strain gradients with respect to the depth, respectively. Results from both samples were in good agreements with the calculation from the coefficient of thermal expansion (CTE) and FEM simulations. Furthermore, the confocal-DIC technique was applied to measure the strain distribution near the chip corner area of a third sample replicating the geometry of a flip chip package. The measured maximum first principal strain was located at the chip corner, reaching 0.9 % at 60 °C, in a good agreement with the simulation results. The strain in front of the crack tip was also evaluated by a three-point bending test in a fourth test sample. The measured maximum strain was 5.8±0.7 %, corresponding to a relative error of only about 5 % compared to simulations for a round crack tip configuration. The averaging used in DIC lowers its spatial resolution and makes it difficult to capture higher strain gradients in small regions. However, the confocal-DIC approach appears to be able to provide reasonable results for evaluating the maximum strain and the full field strain distribution in tri-dimensional volumes with geometries, materials and dimensions which are very similar to those of actual flip chip microelectronic packages.

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Section: Introductionmentioning

confidence: 99%