Effect of temperature on transition in failure modes for high speed impact test of solder joint and comparison with board level drop test

Guruprasad, Pradosh; Pitarresi, James M.

doi:10.1109/ectc.2010.5490685

Cited by 4 publications

(1 citation statement)

References 6 publications

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“…INTRODUCTION Due to the proliferation of electronic devices across the market segments, ranging from the automotive industry to small, portable electronic devices are constantly subjected to high stresses and strains which are induced due to thermal or mechanical shocks resulting from physical handling or their usage other than merely temperature cycling [1][2]. Currently, portable electronic devices such as cell phones personal digital assistants (PDA) and digital camera have an increasing tendency for miniaturization, light weight, high speed, and multifunction, which result in the higher density and smaller dimensions of electronic package.…”

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confidence: 99%

Drop failure modes of a wafer-level chip-scale packaging

Huang

Liu

Zhao

et al. 2013

2013 14th International Conference on Electronic Packaging Technology

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The present work evaluated the board level reliability of a kind of wafer-level chip-scale packaging (WLCSP). Drop impact tests were conducted to evaluate the lifetime and failure mode of the components before and after thermal cycles from -55 to 125 o C (50, 100, 150 temperature cycles) and high temperature (125 o C) storage (50 h, 100 h, 150 h). Under the peak acceleration of 1500 g and pulse duration of 0.5 ms, no failures were found in all of the components experienced thermal treatments after 300 drops. For the components without thermal treatments, cracks generated after 5000 drops under the shock condition with the peak acceleration of 2900 g and the pulse duration of 0.3 ms. Three kinds of failure modes were observed. The first was resin crack that generated between Cu pad and PCB; the second was internal cracks in the solder joints which generated near the IMC layer on the component side; and the third one was fracture of the Cu pad near the component. Among the above three failure modes, resin cracks most likely occurred during drop tests. The solder joints in the first row that closed to the center of PCB were checked after drop tests. Resin cracks were generally emerged at the two corners of the components. The internal cracks of solder joints tended to occur in the third solder joints, due to the resin cracks in the first and second joints released the impact energy. The cracks in Redistribution Layer (RDL) and fracture of Cu pad near the component least happened and always coexisted with the other two kinds of cracks. From the perspective of locations of components, cracks more easily generated in the components near the edge of PCB.Keywords-Sn-3Ag-0.5Cu solder joint; board-level drop reliability; failure mode; wafer-level chip-scale packaging (WLCSP); intermetallic compound (IMC)

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confidence: 99%