Effect of Sn Grain Orientation on Reliability Issues of Sn-Rich Solder Joints

Shen, Yu-An; Wu, John A.

doi:10.3390/ma15145086

Cited by 13 publications

(3 citation statements)

References 108 publications

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“…Void formations can be observed in the following three stages. First, the numerous Cu atoms diffusing into the Sn lattice from the Cu film are via interstitial diffusion, which has a lower energy barrier than vacancy diffusion [36], resulting in rapid Cu diffusion into Sn [37]. This causes considerable vacancies to exit near the Cu site after Cu diffusion into the Sn lattice.…”

Section: Resultsmentioning

confidence: 99%

Void-free interface between in and high-impurity Cu joint

Lee,

Shen,

Chen

2023

Science and Technology of Welding and Joining

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The effect of impurities in the Cu film on the void formation at the interface of the Sn-rich solder joint has been extensively studied. However, this has rarely been studied for In solder joints. In this study, Sn-3.0Ag-0.5Cu (SAC305) and In-solder/ Cu films with high impurities were aged at 150 °C to analyze the films at various aging times. A metastable CuIn 2 phase appeared and transformed into a stable Cu 11 In 9 phase. Noticeable voids and cracks were observed at the SAC305/Cu interface during the solid-state aging. In contrast, there was a void-free interface between In and Cu-CP. This was primarily due to the difference in diffusion behaviour between In/Cu and SAC305/Cu. The mechanism of the above phenomenon was revealed.

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Section: Resultsmentioning

confidence: 99%

Void-free interface between in and high-impurity Cu joint

Lee,

Shen,

Chen

2023

Science and Technology of Welding and Joining

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“…As a result, various signal integrity (SI) and power integrity (PI) issues can arise. In particular, when the noise couples to vertical interconnects such as through glass vias (TGVs), the SI/PI can be degraded even more at solder joints and micro-bumps [17,18] underneath TGVs due to dimensional mismatches. Various types of noise sources that can cause power/ground noise in the glass interposer PDN are depicted in Figure 2.…”

Section: Figurementioning

confidence: 99%

Electrical Performance Analysis of High-Speed Interconnection and Power Delivery Network (PDN) in Low-Loss Glass Substrate-Based Interposers

Kim

2023

Micromachines

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In this article, electrical performance analysis of high-speed interconnection and power delivery network (PDN) in low-loss glass substrate-based interposers is conducted considering signal integrity (SI) and power integrity (PI). The low-loss glass substrate is a superior alternative to silicon substrate in terms of high-speed signaling and fabrication yield. However, the low-loss of the substrate is vulnerable to power/ground noise in the PDN since the low-loss property of the substrate cannot suppress the noise naturally. In this article, an in-depth electrical performance analysis is conducted based on various measurements and simulations to fully benefit the advantages of the low-loss glass substrate. First, the fabrication process and test vehicles for the analysis are explained. Using the test vehicles, the electrical performance of the glass interposer’s high-speed interconnection is compared with those of silicon and organic interposers. The insertion loss, eye-diagrams, and signal bandwidths of three interposer channels are compared and analyzed based on electromagnetic (EM) and circuit simulations. Also, the electrical performance of the through glass via (TGV) channel is measured and compared with through silicon via (TSV) channel. The high-speed interconnection of the glass interposer showed better performance for most of the parameters which is more suitable for maintaining the SI. Even though the low-loss of the glass substrate ensured the SI, power/ground noise issues in the PDN must be analyzed and solved. In this article, various cases inducing the power/ground noise in the PDN are considered, simulated, and measured. To solve the issues, ground TGV design and electromagnetic bandgap (EBG) design are proposed for an efficient broadband suppression of the noise generated in the glass interposer PDN.

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“…Arfaei et al 11 reported longer thermal fatigue life for joints containing β-Sn grains with interlaced morphology compared with beachball morphology. Various authors [12][13][14][15] have noted the importance of CTE mismatch at grain boundaries in damage development in multigrain joints, but these have not quantitatively linked the different orientations within joints to the local CTE mismatch and subsequent damage. At the same time, microstructurally motivated models have been developed [16][17][18][19] to investigate microstructural effects on failure mechanisms and damage evolution in joints subject to thermal cycling and/or shear stress.…”

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confidence: 99%

The role of microstructure in the thermal fatigue of solder joints

Xian,

Xu,

Stoyanov

et al. 2024

Nat Commun

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Thermal fatigue is a common failure mode in electronic solder joints, yet the role of microstructure is incompletely understood. Here, we quantify the evolution of microstructure and damage in Sn-3Ag-0.5Cu joints throughout a ball grid array (BGA) package using EBSD mapping of localised subgrains, recrystallisation and heavily coarsened Ag3Sn. We then interpret the results with a multi-scale modelling approach that links from a continuum model at the package/board scale through to a crystal plasticity finite element model at the microstructure scale. We measure and explain the dependence of damage evolution on (i) the β-Sn crystal orientation(s) in single and multigrain joints, and (ii) the coefficient of thermal expansion (CTE) mismatch between tin grains in cyclic twinned multigrain joints. We further explore the relative importance of the solder microstructure versus the joint location in the array. The results provide a basis for designing optimum solder joint microstructures for thermal fatigue resistance.

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Effect of Sn Grain Orientation on Reliability Issues of Sn-Rich Solder Joints

Cited by 13 publications

References 108 publications

Void-free interface between in and high-impurity Cu joint

Void-free interface between in and high-impurity Cu joint

Electrical Performance Analysis of High-Speed Interconnection and Power Delivery Network (PDN) in Low-Loss Glass Substrate-Based Interposers

The role of microstructure in the thermal fatigue of solder joints

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