Effect of sidewall spacer thickness on hot-carrier degradation of PMOS transistors

Abstract

The effect of the sidewall spacer thickness on the hot-carrier degradation of sidewall-offset single drain PMOS transistors was studied. At the stress bias condition of maximum gate current, a large degradation was observed when there is no overlap between gate and drain. The trapping of a large number of electrons in the sidewall oxide spacer is attributed to this. In the off-state, PMOS transistors were degraded by electrons generated by the band-to-band tunnelling process. Transistors with no gate-to-drain overlap show linle degradation at relatively low V,. because of the small drain leakage current by band-to-band tunnelling. However, as V, is increased and the drain leakage current reaches a certain level, the degree of degradation drastically increases. As in the case of the DC stress test at the peak gate current, this is probably a result of enhanced trapping of injected electrons in the sidewall spacer. These results suggest that there should be an overlap between gate and drain but that the overlap distance should be kept to a minimum in order to maximize t h e hotcarrier resistance of PMOSFETS. The single drain PMOS transistor with the optimum sidewall spacer thickness has a lifetime which is much longer than 10 years at an 1 operation voltage of -3.3V.