Effect of patterning on thermal agglomeration of ultrathin silicon-on-insulator layer

Ishikawa, Yasuhiko; Kumezawa, Minoru; Nuryadi, Ratno; Tabe, Michiharu

doi:10.1016/s0169-4332(01)00833-9

Cited by 33 publications

(36 citation statements)

References 13 publications

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“…Even after 15 h of heating the sample the resistance measured between the bulk Si and the SOI film was unmeasurably large (у50 M⍀), i.e., temperatures of 800°C should not be exceeded in long time annealing steps. Similiar etching processes below 1000°C have been observed also by Ishikawa et al 4 Interestingly, they used UNIBOND® SOI material, too. FIG.…”

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confidence: 58%

Roughness and stability of silicon on insulator surfaces

Czubanowski

Tegenkamp

Ernst

et al. 2004

Applied Physics Letters

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The feasibility of low temperature processes (below 800 °C) to obtain in situ atomically clean and smooth surfaces on (100) oriented silicon on insulator material (SOI) with negligible variation of the top Si film thickness was tested. These steps were characterized using low-energy electron diffraction and atomic force microscopy supplemented by conductivity measurements. The most promising method for obtaining atomically smooth and continuous SOI films is the evaporation of Si at 750 °C at a flux of 0.15 ML/min. For lower rates [113]-oriented pits are formed within the SOI layer. It turned out that mobile and volatile oxide formation at the Si/SiO2 interface in these materials can occur already at temperatures below 1000° C, leading to the destruction of the buried oxide layer.

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confidence: 58%

Roughness and stability of silicon on insulator surfaces

Czubanowski

Tegenkamp

Ernst

et al. 2004

Applied Physics Letters

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“…For each diameter, five repetitions of the same pattern are produced. In the first case (without initial hole shown inFigure 4eleft panel), the annealing leads to the formation of silicon resonators only for the smallest patterns (2.5 μm in diameter) with a poor control and poor spatial localization,36 while for larger sizes (diameters larger than 3 μm), it does not lead to the formation of MRs in 14 structures out of 15 (93%). In the second case (with an initial hole at the center of the enclosed area;Figure 4eright panel), the dewetting leads to the deterministic formation of individual Si-resonators with a high reliability (95%).…”

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confidence: 99%

Wafer Scale Formation of Monocrystalline Silicon-Based Mie Resonators via Silicon-on-Insulator Dewetting

et al. 2014

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Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers.

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“…However, it has been shown that such ultrathin Si layers on SiO 2 are thermally unstable, agglomerating into Si islands upon ultrahigh vacuum ͑UHV͒ annealing. [1][2][3][4][5][6][7][8] The report on thermal agglomeration by Ono et al 1 showed that randomly formed Si islands are observed when an ultrathin Si layer of separationby-implanted-oxygen wafer is subjected to UHV annealing. Several other groups reported island formation for either crystalline or amorphous ultrathin Si layers on SiO 2 .…”

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confidence: 99%

“…[2][3][4][5][6][7][8] In particular, our group reported an ordered formation of islands in the ͗310͘ directions for the ͑001͒ Si layer of bonded SOI wafer. [5][6][7] This ordering property led us to further investigate the applicability to the quantum dot array through patterning of the Si layer. 8 Nonetheless, as revealed in the present study, the agglomeration of Si layer does not necessarily result in deformation into islands.…”

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confidence: 99%

Thermally-induced formation of Si wire array on an ultrathin (111) silicon-on-insulator substrate

Burhanudin

Nuryadi

Ishikawa

et al. 2005

Applied Physics Letters

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We have found that a Si wire array is formed by thermal agglomeration of an ultrathin (111) Si layer in a bonded silicon-on-insulator (SOI) structure, although previous studies for crystalline and amorphous Si layers on SiO2 only showed island formation. As starting material, (111) bonded SOI wafers with the top Si layers thinned to 5–9 nm were used. The samples were then subjected to a thermal treatment at 950 °C in an ultrahigh vacuum. Atomic force microscopy revealed that the (111) top Si layer is deformed into three sets of wire arrays in the three equivalent ⟨112¯⟩ directions. It is also shown that the patterning of a Si layer leads to the wire array selectively formed in one of these three directions.

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Effect of patterning on thermal agglomeration of ultrathin silicon-on-insulator layer

Cited by 33 publications

References 13 publications

Roughness and stability of silicon on insulator surfaces

Roughness and stability of silicon on insulator surfaces

Wafer Scale Formation of Monocrystalline Silicon-Based Mie Resonators via Silicon-on-Insulator Dewetting

Thermally-induced formation of Si wire array on an ultrathin (111) silicon-on-insulator substrate

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