Effect of Oxide Thickness Variation in Sub-micron NMOS Transistor

Dynamic random access memory (DRAM) plays a crucial role as a memory device in modern computing, and the high-k/metal gate (HKMG) process is essential for enhancing DRAM’s power efficiency and performance. However, integration of the HKMG process into the existing DRAM technology presents complex and time-consuming challenges. This research uses machine learning analysis to investigate the relationships among the process parameters and electrical properties of HKMG in DRAM. The expectation–maximization imputation was utilized to fill in the missing data, and the Shapley additive explanations analysis was employed for the regression models to predict the electrical properties of HKMG. The impact of the process parameters on the electrical properties is quantified, and the important features that affect the performance of the HKMG transistor are characterized by using the explainable AI algorithm.

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Effect of Oxide Thickness Variation in Sub-micron NMOS Transistor

Cited by 4 publications

References 17 publications

“Device Design of 30 and 10 nm Triple Gate Single Finger Fin-FET for on Current (ION) and off Current (IOFF) Measurement”

“Device Design of 30 and 10 nm Triple Gate Single Finger Fin-FET for on Current (ION) and off Current (IOFF) Measurement”

Performance Analysis of DGFET, MESFET, and SOI on Varying Device Intrinsic Input Parameters

Machine learning investigation of high-k metal gate processes for dynamic random access memory peripheral transistor

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