2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) 2010
DOI: 10.1109/smelec.2010.5549578
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Effect of oxide thickness on 32nm Pmosfet reliability

Abstract: Negative Bias Temperature Instability (NBTI) has become one of the critical reliability concerns as scaling down CMOS technology especially on the pMOSFET device. A simulation study had been conducted on 32 nm conventional pMOSFET using the technology CAD (TCAD) Sentaurus Synopsys simulator tool. In this paper, the effects of the gate oxide thickness together with drain bias variations on the NBTI are studied. The effect on the device parameters such as interface traps concentration (N it ), threshold voltage … Show more

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Cited by 4 publications
(3 citation statements)
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“…From (21) we see that as the oxide layer gets thinner, tan δ decreases, and from (22), the conductivity decreases in the process, leading to an increase in |S 11 | as seen in the experiment. Ismail et al [27] studied the reflection characteristics of dielectric substrates having a variety of relative permittivity and loss tangent values, and reported that samples with higher ε and loss tangent absorb more incident signal.…”
Section: Variation With Oxide Layer Thicknesssupporting
confidence: 55%
See 1 more Smart Citation
“…From (21) we see that as the oxide layer gets thinner, tan δ decreases, and from (22), the conductivity decreases in the process, leading to an increase in |S 11 | as seen in the experiment. Ismail et al [27] studied the reflection characteristics of dielectric substrates having a variety of relative permittivity and loss tangent values, and reported that samples with higher ε and loss tangent absorb more incident signal.…”
Section: Variation With Oxide Layer Thicknesssupporting
confidence: 55%
“…The interface trapped charges are positive or negative charges, created due to structural defects, oxidation-induced defects, metal impurities, or other defects caused by radiation or similar bondbreaking processes [20]. These trapped charges are located at the Si-SiO 2 interface, whereby their concentration increased with the oxide thickness [21]. This could be explained by the fact that more holes were attracted towards the Si/SiO 2 interface as the oxide thickness decreases.…”
Section: Variation With Oxide Layer Thicknessmentioning
confidence: 99%
“…They plotted N il against the gate oxide thickness and concluded that it increases as the oxide thickness decreases. Other researchers[14] also reported the same and concluded that more holes were attracted towards the Si/SiOz interface as the oxide thickness decreases. Thus, the inversion holes weaken the Si-H bonds and lead to the interface trap creation…”
mentioning
confidence: 53%