In this paper, we address the effect of plasma nitridation on the gate dielectric in terms of device characteristics of an NMOS/PMOS transistor. Firstly, boron segregation due to plasma nitridation near Si/SiO 2 interface and bulk Si is experimentally characterised by 1D SIMS, and its profile is reproduced in simulation of which parameters for boron diffusion are accurately calibrated through a comprehensive calibration process. Secondly, the electrical behaviour of NMOS/PMOS transistor with plasma nitride gate dielectric is verified, observing uncommon behaviour of C-V diagram in the case of buried-channel PMOS transistor. We prove that an excessive amount of interface traps generated by plasma nitridation influence abnormal electrical behaviour of the NMOS/ PMOS transistor.