Effect of lead frame material on plastic-encapsulated IC package cracking under temperature cycling

Nishimura, A.; Kawai, Sueo; Murakami, Gen

doi:10.1109/33.49027

Cited by 40 publications

(10 citation statements)

References 11 publications

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“…The left hand side of (4) was determined from the pressure cell experiment, while the right hand side was calculated using the Young's modulus of the dry MC measured at 0.2 mm/min (see Section II-C) and the Young's modulus of Alloy 42: GPa [15]. The Poisson's ratio was assumed to be 0.33 for both materials.…”

Section: The Boundary Conditionmentioning

confidence: 99%

On the mode II popcorn effect in thin packages

Alpern

Dudek

Schmidt

et al. 2002

IEEE Trans. Comp. Packag. Technol.

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Experiments were carried out using P-TQFP-176 packages to study the mode II popcorn effect in thin packages. The doming of the package backside was measured as a function of time and temperature. The measurements were performed using a line projection method. An "accelerated" increase in the doming was found to correlate with the onset of the package crack propagation. It was shown that when a constant critical doming angle is reached, package cracks begin to propagate toward the surface. This critical doming angle was found to be temperature independent between 170°C and 215°C. Furthermore the development of the package doming with time was described by a simple model based on the moisture diffusion from molding compound and die-attach material in combination with a bimaterial plate theory. The water content of the die-attach layer after preconditioning was calculated from the model and it was found to be in good agreement with the results of a three dimensional finite element simulation

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Section: The Boundary Conditionmentioning

confidence: 99%

On the mode II popcorn effect in thin packages

Alpern

Dudek

Schmidt

et al. 2002

IEEE Trans. Comp. Packag. Technol.

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Section: Informationmentioning

confidence: 99%

“…If all interfaces in the package had perfect adhesions and the stresses were small, delamination was unlikely to occur. However, CTE mismatches between material couples, improper package structures, un-optimized process settings and extreme application environment with humidity or temperature cycling may result into strong interface stresses and package delamination [5][6][7][8][9][10][11][12][13].Some researchers used the method of finite element analysis (FEA) to predict the occurrence of delamination under different conditions. Interface shear stress or strain, von Mises stress, J-integrate and energy release rate were usual indicators to assess the delamination [5,[7][8][9][10][11]14].…”

mentioning

confidence: 99%

Effects of alternating thermal stress on delamination between die attach and leadframe in SOIC package

Zong¹,

Wang²,

Xu³

et al. 2013

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

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Delamination was a critical failure to the microelectronics products, and it was introduced mainly by two factors: strong interface stress or poor interface adhesion. In this paper a tracking experiment confirmed the delamination between die attach and leadframe flag in a SOIC device, which occurred during wire bonding. Results of actual experiments and FEA found during the process flow, there were changes of structure profile as well as von Mises stress at the edge of die attach layer. This alternating stress was introduced by temperature cycling during D/A curing, wire bonding and following cooling; and resulted into the delamination at the interface, whose occurrence could be reduced when a higher peak temperature of D/A curing, a lower temperature of wire bonding, a thicker BLT or a CTE-lower die attach was applied. With a balance between delamination and other items, a final solution was proposed and got perfect results. InformationDue to the demands of higher integration level, higher power and lower cost in electronics industry, packaging technology and materials faced more and more challenges. Delamination was one common and critical failure, which may bring great destroys to the package [1-5]; such as die crack, wire bond lift or break, thermal and electrical performance degradation. If all interfaces in the package had perfect adhesions and the stresses were small, delamination was unlikely to occur. However, CTE mismatches between material couples, improper package structures, un-optimized process settings and extreme application environment with humidity or temperature cycling may result into strong interface stresses and package delamination [5][6][7][8][9][10][11][12][13].Some researchers used the method of finite element analysis (FEA) to predict the occurrence of delamination under different conditions. Interface shear stress or strain, von Mises stress, J-integrate and energy release rate were usual indicators to assess the delamination [5,[7][8][9][10][11]14]. While there were few papers about the effects of processes prior to molding on package delamination. This paper focused on the package delamination occurring before molding at the interface between die attach and leadframe flag. The results of actual experiments and FEA found the alternating interface stress, introduced by CTE mismatch and temperature cycling prior to molding, resulted into this delamination. At the same time, effects of some process factors were studied and a final solution was proposed to solve this delamination. BackgroundDuring the characterization of one small outline 28ld non exposed pad device, the package delamination between die attach and leadframe flag was found with through-scan CSAM

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“…Cu-based leadframe materials have such advantages as higher electrical and thermal conductivity and lower cost compared with Alloy 42 [3]. The use of Cu-based leadframe materials in power devices and logic chips, where heat dissipation capacity is a more serious consideration, has become popular.…”

Section: Introductionmentioning

confidence: 99%

Experimental determination of interfacial toughness curves

Lee

2002

Met. Mater. Int.

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The evaluation of mixed-mode interfacial fracture toughness is of great importance for the integrity of electronic devices because interfacial cracks are subjected to mixed-mode loading by vapor pressure, thermal stress and other factors. A lot of work has been done to clarify the unusual characteristics of the fracture of bimaterial interfaces. Since interfacial fracture toughness (G C ) greatly depends on phase angle (ψ), most work has focused on the determination of G C -ψ curves using various specimens. However, this requires a lot of time, expense and effort. In this work, the G C -ψ curves of oxidized Cu-based leadframe/EMC (epoxy molding compound) interfaces were determined by measuring interfacial fracture toughness under mode-I, mode-II and mixed-mode loading conditions using sandwiched-double-cantilever-beam (SDCB) specimens, Arcan specimens and sandwiched-Brazilian-nut (SBN) specimens, respectively. The experimental results showed that the measured G C -ψ curves obeyed the G C -ψ expression proposed by Ahmad first developed by Evans and Hutchinson based on the micromechanics modeling of mixed-mode fracture. Comparing data in the literature, the G C -ψ expression proposed by Ahmad was confirmed to be valid, and a method of predicting G C -ψ curves without much experiment was proposed.

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Effect of lead frame material on plastic-encapsulated IC package cracking under temperature cycling

Cited by 40 publications

References 11 publications

On the mode II popcorn effect in thin packages

On the mode II popcorn effect in thin packages

Effects of alternating thermal stress on delamination between die attach and leadframe in SOIC package

Experimental determination of interfacial toughness curves

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