Effect of Interrupt Logic on Delay Balancing Circuit

Kumar, N. Suresh; Reddy, D V Rama Koti

doi:10.5120/3288-4479

Cited by 4 publications

(1 citation statement)

References 9 publications

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“…To study the present method a DC motor is taken into consideration for testing. The new method can also be adoptable to different applications like fiber optics [20], [21], signal processing, and computer architecture [22], and linear model frequency measurement [23]. The prototype of DC motor with Tachometer is interfaced with FPGA board [24].…”

Section: Existing Techniquesmentioning

confidence: 99%

A new method for self-organized dynamic delay loop associated pipeline with reconfigurable computing system

Kumar

Lakshmi

Prasanna

et al. 2022

IJECE

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<span>The minimization of propagation delay between pipeline stages is very important in wave propagation through pipeline-stages. The propagation delay can be minimized by minimizing the number of stages in a pipeline. In the proposed design a dynamic stage control is imparted in the pipeline. The propagation delay can be optimized in any type of pipeline by controlling number of stages dynamically. The pipeline interpretation helps a lot to overcome the flaws due to not ready sequence (NRS) and synchronization problems. It is observed that, in the pipeline design the basic and actively involved pipeline techniques are concerned with different challenges like clock, throughput, cell area, and sizes. As the data throughput increases the number of stages in pipeline also needs to be increased to meet the desired goal. In the case of unpredictable data speed, the definite number of pipeline stages creates severe problems. In this work a dynamic pipeline is integrated where the number of stages is dynamically changing depending up on data speed. In dynamic pipeline technique the circuit cell area of reconfigurable computing system (RCS) will be reduced dynamically at low-speed data transmission. In the high-speed data communication, the data speed is managed and controlled by dynamic delay loops.</span>

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Section: Existing Techniquesmentioning

confidence: 99%

A new method for self-organized dynamic delay loop associated pipeline with reconfigurable computing system

Kumar

Lakshmi

Prasanna

et al. 2022

IJECE

View full text Add to dashboard Cite

show abstract

Design and analysis for improving reliability and accuracy of big-data based peripheral control through IoT

Rani¹,

Geetavani²

2017

2017 International Conference on Trends in Electronics and Informatics (ICEI)

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Studies and a Method to Minimize and Control the Jitter in Optical Based Communication System

Kumar¹,

Sridevi²,

Reddy³

et al. 2013

IJACSA

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Abstract-In the years, optical communication systems have been using significantly for attractive solutions to the increasing high data rate in telecommunication systems and various other applications. In the present days mostly, two types of communication schemes are using in data communication, namely asynchronous transmission and synchronous transmission depending on their timing and frame format. But both transmission systems are facing complications seriously with the involvement of jitter in data propagation. The jitter can degrade the performance of a transmission system by introducing bit errors and uncontrolled offsets or displacements in the digital signals. The jitter creates problems furiously at high data rate systems. The jitter need to be minimized in the communication system, otherwise it also degrades the performance of the interconnected systems with main circuit. This will happen due to improper synchronization or management of the clock scheme in the communication system. The improper organization of clock scheme propagates fault data and clock scheme to all other interconnected circuits. In the present work a new clock scheme is discussed to minimize the jitter in data propagation.

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Effect of Interrupt Logic on Delay Balancing Circuit

Cited by 4 publications

References 9 publications

A new method for self-organized dynamic delay loop associated pipeline with reconfigurable computing system

A new method for self-organized dynamic delay loop associated pipeline with reconfigurable computing system

Design and analysis for improving reliability and accuracy of big-data based peripheral control through IoT

Studies and a Method to Minimize and Control the Jitter in Optical Based Communication System

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