Effect of ELA Energy Density on Self-Heating Stress in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Huang, Sheng-Lung; Chen, Hong-Chih; Chen, Po-Hsun; Zheng, Yu‐Zhe; Chu, Ann-Kuo; Shih, Yu‐Shan; Wang, Yu-Xuan; Wu, Chia‐Ching; Chen, Yuan; Sun, Pei-Jun; Huang, Hui‐Chun; Lai, Wei-Chih; Chang, Ting‐Chang

doi:10.1109/ted.2020.3005366

Cited by 10 publications

(6 citation statements)

References 21 publications

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“…Furthermore, low-temperature laser annealing can be used instead of the SPC and RTA process to reduce the process temperature and facilitate the process z E-mail: williammaa@mail.ee.nsysu.edu.tw ECS Journal of Solid State Science and Technology, 2023 12 055006 integration of 3D-IC. 26,27 The channel width and length of poly-Si FeT-TFT discussed in this work are 100 and 10 μm, respectively.…”

Section: Methodsmentioning

confidence: 99%

Ferroelectric Tunnel Thin-Film Transistor for Synaptic Applications

Cheng-Yu¹,

Su²,

Kao³

et al. 2023

ECS J. Solid State Sci. Technol.

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A ferroelectric tunnel thin-film transistor (FeT-TFT) with polycrystalline-silicon (poly-Si) channel and ferroelectric HfZrOx gate dielectric is demonstrated with analog memory characteristics for the application of synaptic devices. The FeT-TFT exhibits a much lower conduction current of ~0.032 times in transfer characteristics and maximum conductance (Gd) of ~0.14 to 0.2 times in potentiation and depression operation than the FeTFT due to FeT-TFT’s carrier transport mechanism: interband tunneling. This work employed pulse widths of 75, 150, and 300 ns to modulate Gd, and it was found that using a pulse width of 75 ns could achieve low asymmetry ~1 and high Gd ratio ~20.63 under consideration of operation speed. When the pulse time is increased, the potentiation and depression voltages can be significantly decreased to maintain the low asymmetry, but the Gd ratio is also reduced. In addition, the endurance characteristic of poly-Si FeT-TFT is found to be strongly related to the degradation effect of subthreshold swing due to the dynamic stress effect in the endurance measurement. This result reveals that the reliability of ferroelectric devices is not only owing to the degradation of the remanent polarization.

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Section: Methodsmentioning

confidence: 99%

Ferroelectric Tunnel Thin-Film Transistor for Synaptic Applications

Cheng-Yu¹,

Su²,

Kao³

et al. 2023

ECS J. Solid State Sci. Technol.

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“…The D it and DOS analysis results explain the degradation phenomenon. Charge trapping is one of the dominant degradation mechanisms in NBTI [20,21]. The probability of charge trapping is a proportional to the number of carriers and defects.…”

Section: Reliability Under Nbti and Hcimentioning

confidence: 99%

“…However, it is difficult to explain the ∆V th trend for flexible LTPS TFTs with different T a values because of the variations in other reliability-related factors in addition to the defect states in the semiconductor layer. In LTPS TFTs, the charge-trapping phenomenon is affected by the trap sites in the gate insulator and the hydrogen density in the dielectric layers adjacent to the active layer [20,21]. Because T a can affect these factors, the ∆V th of flexible LTPS TFTs with different T a values is difficult to explain only by the defect states in the active layer.…”

Section: Reliability Under Nbti and Hcimentioning

confidence: 99%

Electrical-performance and reliability improvement of flexible low-temperature polycrystalline silicon thin-film transistors via post-annealing process

Im¹,

Ahn²,

Kim³

et al. 2022

Semicond. Sci. Technol.

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We investigated the improvement methods of the electrical characteristics and reliability of flexible low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) by optimizing the annealing process. We investigated the effect of annealing on the device properties via electrical measurement and density-of-state (DOS) analysis. The annealing temperature should be reduced for flexible LTPS TFTs compared to rigid devices because the range of the thermal stability of flexible substrate is narrower than that of the glass substrate. As the activation annealing temperature (Ta) decreased, the threshold voltage and field-effect mobility (μFE) decreased, and the subthreshold swing (SS) increased. When the post-annealing temperature (Tpa) decreased, μFE increased, and the changes in the other parameters were negligible. The DOS decreased with an increase in Ta and a reduction in Tpa. These results originated from ineffective dopant activation and defect curing due to the lower Ta and the enhanced hydrogen defect passivation at the lower Tpa. Therefore, flexible LTPS TFTs with reduced Ta values exhibited similar μFE values and lower SS values when the post-annealing process was omitted. Furthermore, removing the post-annealing process improved the reliability of the flexible LTPS TFTs with reduced Ta values under electrical stress. According to a hot-carrier instability analysis, defect passivation by hydrogen was more stable than defect curing with a higher Ta. Consequently, although Ta was low for flexible LTPS TFTs, the electrical performance and reliability could be improved by optimizing the post-annealing process.

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“…This makes it challenging to apply them to largescreen displays. 4,5 In contrast, AOS TFTs, while having relatively lower mobility compared to LTPS TFTs, exhibit excellent process uniformity, low processing temperatures, and low off-state current. 6−8 The recent trend in ultrahighresolution (UHR) displays is not only focused on increasing pixels per inch (PPI) but also on reducing power consumption due to the increase in the number of transistors for driving the high pixel density.…”

Section: ■ Introductionmentioning

confidence: 99%

Thermal Dehydrogenation Impact on Positive Bias Stability of Amorphous InSnZnO Thin-Film Transistors

Lee,

Song,

Park

et al. 2024

ACS Appl. Mater. Interfaces

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Effect of ELA Energy Density on Self-Heating Stress in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Cited by 10 publications

References 21 publications

Ferroelectric Tunnel Thin-Film Transistor for Synaptic Applications

Ferroelectric Tunnel Thin-Film Transistor for Synaptic Applications

Electrical-performance and reliability improvement of flexible low-temperature polycrystalline silicon thin-film transistors via post-annealing process

Thermal Dehydrogenation Impact on Positive Bias Stability of Amorphous InSnZnO Thin-Film Transistors

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