Effect of a Two-Step Recess Process Using Atomic Layer Etching on the Performance of $\hbox{In}_{0.52}\hbox{Al}_{0.48}\hbox{As/In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ p-HEMTs

Abstract

The characteristics of 0.15-µm InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-HEMTs) that were fabricated using the Ne-based atomic layer etching (ALET) technology and the Ar-based conventional reactive ion etching (RIE) technology were investigated. As compared with the RIE, the ALET used a much lower plasma energy and thus produced much lower plasma-induced damages to the surface and bulk of the In 0.52 Al 0.48 As barrier and showed a much higher etch selectivity (∼70) of the InP spacer against the In 0.52 Al 0.48 As barrier. The 0.15-µm InAlAs/InGaAs p-HEMTs that were fabricated using the ALET exhibited improved G M,max (1.38 S/mm), I ON /I OFF (1.18 × 10 4 ), drain-induced barrier lowering (80 mV/V), threshold voltage uniformity (V th,avg = −190 mV and σ = 15 mV), and f T (233 GHz), mainly due to the extremely low plasma-induced damage in the Schottky gate area. Index Terms-Atomic layer etching (ALET), drain-induced barrier lowering (DIBL), I ON /I OFF ratio, pseudomorphic highelectron mobility transistor (p-HEMT), subthreshold slope.