EDT bandwidth management - Practical scenarios for large SoC designs

Janicki, Jakub; Tyszer, Jerzy; Cheng, Wu-Tung; Huang, Yu; Kassab, Mark; Mukherjee, Nilanjan; Rajski, J.; Dong, Yanhao; Giles, G.

doi:10.1109/test.2013.6651898

Cited by 13 publications

(4 citation statements)

References 36 publications

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“…The concept of hybrid test is illustrated with an example in Figure 8, where Core 1 and Core 4 each has its own wrapper, but Core 2 and Core 3 are sharing one wrapper. These three wrappers connected to the SoC level pins through TAM (input/output switching network as described in [1]). …”

Section: Hybrid Test Methodologymentioning

confidence: 99%

“…We manually partition these 26 cores into 6 groups (named Group A to Group F) based on their functionalities. The cores in the same group can be test in parallel, but different groups can only be tested in serial, assuming to use some TAMs described in [1] or [9]. Note that in this paper, we do not discuss how to optimally partition the cores into groups.…”

Section: Case Studymentioning

confidence: 99%

“…The most promising and completely scalable test methodology for core-based SoCs is the hierarchical test. In the traditional hierarchical test methodology, ATPG is performed on each wrapped core, and the core-level patterns are mapped to the next level up based on the pattern retargeting technology [1] [2]. Hierarchical test has several benefits compared to running ATPG at the SoC level: (1) ATPG at the core-level can significantly reduce the memory footprint and CPU time compared to running at the SoC-level.…”

Section: Introductionmentioning

confidence: 99%

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Hybrid Hierarchical and Modular Tests for SoC Designs

Li¹,

Qian²,

Yang³

et al. 2015

2015 IEEE 24th North Atlantic Test Workshop

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Modular test and hierarchical test of core-based System-on-Chip (SoC) are two widely used SoC test methodologies. In this paper, the hybrid test methodology that incorporates these two together is studied by using an industrial real case. Thorough experimental results are demonstrated to compare various scenarios of the hybrid hierarchical and modular tests for SoC designs. Based on the experimental results, using channel sharing based modular test technology at a group of cores combined with hierarchical test to map the patterns of core groups to the top level would result in the most efficient total test time. IEEE 24rd North Atlantic Test Workshop978-1-4673-7417-0/15 $31.00

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Section: Hybrid Test Methodologymentioning

confidence: 99%

Section: Case Studymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Hybrid Hierarchical and Modular Tests for SoC Designs

Li¹,

Qian²,

Yang³

et al. 2015

2015 IEEE 24th North Atlantic Test Workshop

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“…The techniques based on Embedded Deterministic Test described in [19,20] employ dynamic channel allocation to manage tester channel bandwidth. They allow multiple cores to be tested simultaneously and allocate tester channels dynamically to decompressors as needed.…”

Section: Introductionmentioning

confidence: 99%

SOC Test Compression Scheme Sharing Free Variables in Embedded Deterministic Test Environment

Wang¹,

Cai²,

Xiang³

2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a new SOC test compression scheme in Embedded Deterministic Test (EDT) compression environment. Compressed test data is brought over the TAM from the tester to the cores in SOC and decompressed in the cores. The proposed scheme allows cores tested at the same time to share some test channels. By sharing free variables in these channels across test cubes of different cores decompressed at the same time, high encoding efficiency is achieved. Moreover, no excess control data is required in this scheme. The ability to reuse excess free variables eliminates the need for high precision in matching the number of test channels with the number of care bits for every core. Experimental results obtained for some SOC designs illustrate effectiveness of the proposed test application scheme.

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Software-based test and diagnosis of SoCs using embedded and wide-I/O DRAM

Deutsch

Chakrabarty

2015

The 20th Asia and South Pacific Design Automation Conference

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EDT bandwidth management - Practical scenarios for large SoC designs

Cited by 13 publications

References 36 publications

Hybrid Hierarchical and Modular Tests for SoC Designs

Hybrid Hierarchical and Modular Tests for SoC Designs

SOC Test Compression Scheme Sharing Free Variables in Embedded Deterministic Test Environment

Software-based test and diagnosis of SoCs using embedded and wide-I/O DRAM

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