EDT Bandwidth Management in SoC Designs

Janicki, Jakub; Kassab, Mark; Mrugalski, Grzegorz; Mukherjee, Nilanjan; Rajski, J.; Tyszer, Jerzy

doi:10.1109/tcad.2012.2205385

Cited by 17 publications

(9 citation statements)

References 50 publications

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“…Partial scan designs [1] use a selective set of flip-flops to form shift registers. The flip-flops are chosen [18], [13] such that they minimize overhead without loss of coverage. BIST…”

Section: Figure 1: Sequential Circuitmentioning

confidence: 99%

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Optimized Test compression for Ultra- large-Scale SoC Architectures performing Scan Test Bandwidth Management

2017

IJMTER

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-With the increase in chip size and complexity, the direct or bus interconnects in conventional SoC test control models are rather restricted. In this paper, we propose a new distributed multihop wireless test control network based on the recent development in -radio-onchip‖ technology. The proposed architecture consists of three basic components, the test scheduler, the resource configurators, and the RF nodes which support the communication between the test scheduler and clusters of cores. Under the multilevel tree structure, the resources (including not only the circuit blocks to perform testing, but also the on-chip radio-frequency nodes for intra-chip communication) are properly distributed and system optimization is performed in terms of both test application time and test control cost. The extension for the project is done by eliminating the clusters of cores, which reduces the area. Simulation and Synthesis is observed by Xilinx ISE 13.2.

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“…Partial scan designs [1] use a selective set of flip-flops to form shift registers. The flip-flops are chosen [18], [13] such that they minimize overhead without loss of coverage. BIST…”

Section: Figure 1: Sequential Circuitmentioning

confidence: 99%

“…3) of this paper comprises two switching networks, as introduced in [13]. An external ATE In channel i (ICi) feeds an In-switching network that reroutes compressed test data to different cores (in the remaining parts of this paper a given core k is denoted as Ck) based on the control data produced by a test scheduler.…”

Section: Figure 2: Bist Implementationmentioning

confidence: 99%

Optimized Test compression for Ultra- large-Scale SoC Architectures performing Scan Test Bandwidth Management

2017

IJMTER

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“…To reduce the test application time, the efficiency of utilizing limited tester bandwidth must be improved. In [24] [25], it was observed that the number of specified bits in the test cubes generated by dynamic compaction is non-uniformly distributed. The tester bandwidth can be reduced through dynamic allocation of the channel inputs feeding different cores in the SoC.…”

Section: Introductionmentioning

confidence: 99%

“…To support this scheme, demutiplexers are inserted between top-level channel inputs and core inputs that allow dynamically configuring the channel inputs feeding each core. In [24], the control data for the demultiplexers is supplied per pattern through the same channel inputs used for shifting the compressed scan stimuli. A cycle-based method was proposed in [25] to allocate the channel inputs.…”

Section: Introductionmentioning

confidence: 99%

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Using dynamic shift to reduce test data volume in high-compression designs

Lin

Kassab

Rajski

2014

2014 19th IEEE European Test Symposium (ETS)

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This paper presents a test data volume (TDV) reduction method for designs utilizing extremely high compression configurations, and it enables reducing the pin count interfacing with the Automatic Test Equipment. Based on the encoding requirements for every test cube, the proposed test compression method changes the number of shift cycles used to load the test stimuli dynamically. No additional pins or modification of the existing scan chains is needed, making the proposed method work seamlessly with existing sequential linear decompressors. Experimental results obtained for industrial designs demonstrate the effectiveness of the proposed method at reducing TDV in high compression configurations.

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Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs

Muthyala

Touba

2015

VLSI-SoC: Internet of Things Foundations

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International audienceThree Dimensional Integrated Circuits are an important new paradigm in which different dies are stacked atop one another, and interconnected by Through Silicon Vias (TSVs). Testing 3D-ICs poses additional challenges because of the need to transfer data to the non-bottom layers and the limited number of TSVs available in the 3D-ICs for the data transfer. A novel test compression technique is proposed that introduces the ability to share tester data across layers using daisy-chained decompressors. This improves the encoding of test patterns substantially, thereby reducing the amount of test data required to be stored on the external tester. In addition, an inter-layer serialization technique is proposed, which further reduces the number of TSVs required, using simple hardware to serialize and deserialize the test data. Experimental results are presented demonstrating the efficiency of the technique proposed

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EDT Bandwidth Management in SoC Designs

Cited by 17 publications

References 50 publications

Optimized Test compression for Ultra- large-Scale SoC Architectures performing Scan Test Bandwidth Management

Optimized Test compression for Ultra- large-Scale SoC Architectures performing Scan Test Bandwidth Management

Using dynamic shift to reduce test data volume in high-compression designs

Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs

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