Edge effects on the TSV array capacitances and their performance influence

Coding Approach for Low-Power 3D Interconnects

“…Since the capacitances of the C matrix are heterogeneous [5,10], the assignment of the logical bits to the TSVs affects the power consumption. Moreover, a fixed inversion of some of the logical bits before the transmission may potentially decrease the T entries.…”

“…overall capacitance C T ,i and vice versa. In TSV arrays, corner TSVs have the lowest overall capacitance, and edge TSVs have a lower overall capacitance than TSVs in the middle of an array [5]. Thus, the optimal assignment maps the bits with the highest self switching to the array corners.…”

“…Therefore, in order to reduce the power consumption, highly correlated bit pairs (large E{∆b i ∆b j }) have to be assigned to TSV pairs connected by a large coupling capacitance. In TSV arrays, the biggest coupling capacitances are located between corner TSVs and their two direct adjacent edge TSVs, due to the reduced E-field sharing effect [5]. MSBs of normally distributed signals have the highest cross-correlation.…”

“…In such systems, the patterns traversing the TSVs are often temporally correlated and/or normally distributed, resulting in bits with different switching properties [18]. We show that these properties can be exploited to effectively reduce the power consumption by an intelligent bit-to-TSV assignment, since the capacitances of TSV arrays are heterogeneous [5]. An additional fixed inversion of some bits before the transmission, realized by using inverting TSV drivers, can further decrease the power consumption, mainly due to the MOS effect.…”

“…metal-wire pair has the same size. In contrast, TSVs have a maximum of eight adjacent neighbors and due to the different distances between direct and diagonal adjacent neighbors, combined with the E-field sharing effect [10], several capacitance values exist in a TSV array [5]. Hence, traditional low-power coding techniques are not directly applicable for TSV arrays.…”