Edge Effects in Bottom-Gate Inverted Staggered Thin-Film Transistors

Mativenga, Mallory; Um, Jae Kwang; Kang, Da Hyun; Mruthyunjaya, Ravi K.; Chang, J. H.; Heiler, Gregory; Tredwell, T.J.; Jang, Jin

doi:10.1109/ted.2012.2205258

Cited by 29 publications

(22 citation statements)

References 15 publications

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“…Then, a 200-nm-thick PECVD SiO 2 layer was deposited at 200 o C as the passivation layer. Finally, the samples were annealed at 250 o C in a vacuum for 2 h as a post annealing step [7], [8]. Most important point, in our fabrication is that the gate dielectric and active layer are deposited without breaking the vacuum in a cluster tools deposition equipment, which eliminates the contamination issues at interfaces, thereby improving device stability and reproducibility.…”

Section: Methodsmentioning

confidence: 99%

P‐7: High Speed a‐IGZO TFT‐based Gate Driver by using Back Channel Etched Structure

Um¹,

Mativenga²,

Geng³

et al. 2014

Symp Digest of Tech Papers

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We demonstrated the high performance back-channel-etched (BCE) amorphous-InGaZnO (a-IGZO) thin-film transistor (TFT) circuits. The TFTs exhibited the field-effect mobility, turn-on voltage and subthreshold swing of 18 cm 2 /V•s, -0.1 V, and 258 mV/dec, respectively. The oscillation frequency of an 11 stages ring-oscillator is ~334.1 kHz, at VDD = 20 V. The 320 stages 11T2C shift-register operated well up to the last stage with rising and falling times of 950 and 690 ns, respectively. Good performance is attributed to damage-free back channel wet etch process and small overlap capacitance between the gate and source/drain electrodes.

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Section: Methodsmentioning

confidence: 99%

P‐7: High Speed a‐IGZO TFT‐based Gate Driver by using Back Channel Etched Structure

Um¹,

Mativenga²,

Geng³

et al. 2014

Symp Digest of Tech Papers

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“…The fabrication process of the BCE TFTs appears elsewhere. 22 On glass substrate, 100 nm molybdenum (Mo) layer was deposited by DC sputtering and patterned as gate electrode. A bilayer of 100 nm SiN x and 150 nm SiO 2 was deposited through plasma enhanced chemical vapor deposition (PECVD) as a gate insulator, followed by deposition of an a-IGZO by sputtering.…”

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confidence: 99%

Control of O-H bonds at a-IGZO/SiO2 interface by long time thermal annealing for highly stable oxide TFT

Jeon

Lee

et al. 2017

AIP Advances

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We report two-step annealing, high temperature and sequent low temperature, for amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) to improve its stability and device performance. The annealing is carried out at 300 oC in N2 ambient for 1 h (1st step annealing) and then at 250 oC in vacuum for 10 h (2nd step annealing). It is found that the threshold voltage (VTH) changes from 0.4 V to -2.0 V by the 1st step annealing and to +0.6 V by 2nd step annealing. The mobility changes from 18 cm2V-1s-1 to 25 cm2V-1s-1 by 1st step and decreases to 20 cm2V-1s-1 by 2nd step annealing. The VTH shift by positive bias temperature stress (PBTS) is 3.7 V for the as-prepared TFT, and 1.7 V for the 1st step annealed TFT, and 1.3 V for the 2nd step annealed TFT. The XPS (X-ray photoelectron spectroscopy) depth analysis indicates that the reduction in O-H bonds at the top interface (SiO2/a-IGZO) by 2nd step annealing appears, which is related to the positive VTH shift and smaller VTH shift by PBTS.

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“…1,2 Inverted staggered structures with an etch stopper have been widely studied for a-IGZO TFTs. [3][4][5] However, this structure suffers from large overlap capacitance between the gate and source/drain electrodes. Large parasitic capacitance induces the signal delay of the TFT array and reduces the operating speed of TFT circuits.…”

mentioning

confidence: 99%

Coplanar amorphous-indium-gallium-zinc-oxide thin film transistor with He plasma treated heavily doped layer

Jeong

Lee²,

Lee³

et al. 2014

Appl. Phys. Lett.

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Edge Effects in Bottom-Gate Inverted Staggered Thin-Film Transistors

Cited by 29 publications

References 15 publications

P‐7: High Speed a‐IGZO TFT‐based Gate Driver by using Back Channel Etched Structure

P‐7: High Speed a‐IGZO TFT‐based Gate Driver by using Back Channel Etched Structure

Control of O-H bonds at a-IGZO/SiO2 interface by long time thermal annealing for highly stable oxide TFT

Coplanar amorphous-indium-gallium-zinc-oxide thin film transistor with He plasma treated heavily doped layer

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