Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in $5~\mu$ s

Shahramian, Shahriar; Dehlaghi, Behzad; Carusone, Anthony Chan

doi:10.1109/jssc.2016.2594209

Cited by 16 publications

(11 citation statements)

References 15 publications

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“…So, the multi-tap FIR DFE consumes a lot of power. The IIR filter that removes multiple post-cursors consumes less power compared to the FIR filter [30,31]. Fig.…”

Section: Iir Filtermentioning

confidence: 99%

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

Kang

Song

2021

IEICE Electron. Express

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This paper describes quad-rate 1-FIR 2-IIR decision feedback equalizer (DFE) with summer reduction technique for high-speed serial communication in a 65nm CMOS technology. The proposed DFE halves the number of summers by using resettable slicer and summer with multiplexer. Therefore, the proposed DFE reduces power consumption significantly because summer dissipates a lot of power. The DFE that is verified by pre-layout simulations achieved 0.69 unitinterval (UI) eye-opening. The proposed DFE that is designed with a 65-nm technology operates at 28Gb/s and occupies 0.023mm 2 . Finally, the power efficiency of the proposed DFE is 0.88-pJ/bit.

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“…So, the multi-tap FIR DFE consumes a lot of power. The IIR filter that removes multiple post-cursors consumes less power compared to the FIR filter [30,31]. Fig.…”

Section: Iir Filtermentioning

confidence: 99%

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

Kang

Song

2021

IEICE Electron. Express

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“…With a thermometer coding which prohibits two‐bit switching, the aforementioned glitch is no longer a concern. However, a one‐bit switching, for example, from

false(1, 0 false)

false(1, 1 false)

, doubles the driving strength then induces non‐linearities and deteriorates the monotonic modulation of the PR [5].…”

Section: Switching Glitches In Prsmentioning

confidence: 99%

“…Introduction: A phase rotator (PR) is a circuit component that is widely used in wireline interface applications such as clock and data recoveries (CDRs) [1][2][3][4][5]. CDRs with a forwarded reference clock require a PR after a multiphase clock generator to recover the clock phase of the data sampling point [2,3,5], thus the performance of such CDRs varies with that of the PR. PRs are commonly realised in the current-mode logic (CML) to achieve high linearity and a wide frequency range.…”

mentioning

confidence: 99%

“…However, such a topology consumes large power owing to the static current and requires a large silicon area due to the passive loads [2][3][4]. Another PR implementation is made up of inverter buffers with configurable driving strength [5]. Although such an inverter-based PR might provide higher efficiency in power and area, it suffers from nonlinear characteristics with switching glitches that might lead to a severe malfunction in CDRs.…”

mentioning

confidence: 99%

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Synthesisable glitch‐less phase rotator with conditionally cascading scheme

2020

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This Letter presents a synthesisable phase rotator (PR) which operates without switching glitches that are reported in conventional implementations. The proposed conditionally cascading PR (CCPR) is comprised of two multiplexers (MUXes) with logic gates, and a phase interpolator (PI). This composition enables the automatic design flow through hardware description language which shortens the design time. With the MUXes operating as a cascaded PI at transition points, the proposed CCPR outputs a clock without any transient anomaly. A remarkable reduction in power and area is achieved by sharing a common PI for every pair of input clocks and merging low pass filters into the MUXes. Simulated in a 40-nm technology, the proposed CCPR consumes 1.9 mW at a 1.1 V supply with 5.4 GHz operation.

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“…On the other hand, the DFE is mostly adapted in digital methods. Recently, adaptation based on the sign-sign least-mean-square (SS-LMS) algorithm has become the most popular scheme, because of its simple implementation [6]- [8].…”

Section: Introductionmentioning

confidence: 99%

A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector

Choi

Hwang²,

Lee

et al. 2021

IEEE Access

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This paper presents an area-and energy-efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate output clock of a digitally controlled oscillator (DCO) for both the equalizer adaptation and clock recovery loop, the proposed adaptive equalizer is combined with the CDR by sharing its adaptation loop including a sub-sampling phase detector (SSPD) and a digital logic circuit. Consequently, the active area and power dissipation for the adaptive equalizer are reduced. Furthermore, the SEC is proposed to improve the high-frequency jitter tolerance of the CDR. The SEC detects bit errors by observing the comparator decision and corrects the errors without any data encoding or complicate circuits. The out-of-band jitter tolerance is improved by 22.6% at 100 MHz for 17.2-dB loss channel with <10 -12 biterror rate (BER) with the proposed SEC. The SEC is applicable to various receivers with compact design at a low cost. The prototype receiver consumes 23.9 mW at 14-Gb/s and occupies 0.007 mm 2 in a 28-nm CMOS technology.INDEX TERMS Adaptive equalizer, clock and data recovery (CDR), continuous-time linear equalizer (CTLE), decision feedback equalizer (DFE), jitter tolerance, receiver, self-error corrector (SEC), subsampling.

show abstract

Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in $5~\mu$ s

Cited by 16 publications

References 15 publications

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

Synthesisable glitch‐less phase rotator with conditionally cascading scheme

A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector

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