Economic effects in design and test

Dear, Ian; Dislis, C.; Ambler, A.P.; Dick, Jochen

doi:10.1109/54.107206

Cited by 33 publications

(3 citation statements)

References 15 publications

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“…For example, a parallel ATPG executing on eight threads still suffers from 15.9% and 10.8% inflation on pattern count for two sample circuits (s38584 from ISCAS'89 and vga-enh from IWLS'05) as Figure 1 illustrates. According to [11], an increase (15.9%) in test patterns can cause a 100% increase in test cost per unit at the worst-case scenario, not to mention the additional test time and the financial loss due to delayed time to market. Hence, test inflation has become a critical problem that limits the practicality of parallel ATPG.…”

Section: Introductionmentioning

confidence: 98%

Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation

Huang

Lin

et al. 2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Multi-core machines enable the possibility of parallel computing in Automatic Test Pattern Generation (ATPG). With sufficient computing power, previously proposed parallel ATPG has reached near linear speedup. However, test inflation in parallel ATPG yet arises as a critical problem and limits its practicality. Therefore, we developed a parallel ATPG system that incorporates (1) concurrent interruption (CI), (2) ripple compaction (RC) and (3) fan-in-cone based fault ordering (FIC) to deal with such problem. Concurrent interruption aborts test generation on simultaneously detected faults by fault simulation. Ripple compaction combines tests for different faults while fan-in-cone based fault ordering strategically arranges the fault list to reduce the number of test generations and thus speeds up the ATPG process. According to our experiments, the proposed parallel ATPG system effectively reduces 11% pattern count and achieves ∼0% test inflation while maintaining an average of 6.5X speedup with no attenuation in fault coverage on experimental circuits. I. . INTRODUCTIONAs VLSI designs continue to grow in size and complexity, the demand for faster ATPG arises for their verification testing. The conventional ATPG algorithm running on single processor has reached its bottleneck and become unsustainable to generate quality tests effectively for modern designs. The rapid development of multi-core processors enables the possibility of parallel computing and emerges to be a solution for scaled designs. By its communication protocol, a parallel computing architecture can be classified into: shared-memory system and message-passing system. Both parallel computing systems provide additional computing power and thus are used in [1] [2][10] to speed up ATPG recently.Common strategies used in parallel ATPG include fault parallelism, heuristic parallelism, search-space parallelism, algorithmic parallelism, and circuit parallelism. Fault parallelism [4] divides all faults among available processors and each processor generates tests for its corresponding faults. For heuristic parallelism [5], each processor employs a distinctive ATPG algorithm to generate a test for the same fault. Search-space parallelism [5] allows the processors to work collectively in finding a test for a single fault by dividing search space into discrete pieces and let each processor work on these search spaces simultaneously. ATPG algorithms are divided into fine- Fig. 1. Test-inflation problem in parallel ATPG grained tasks and processors work in parallel on each task in algorithmic parallelism [6]. For circuit parallelism [7], the circuit is divided into disjoint sub-circuits and each processor will perform ATPG operations on its respective part.Although various parallelism approaches were proposed, the core of parallel ATPG does not vary with these approaches and involves only two major operations: test generation and fault simulation. Krishnaswamy et al. in [8] parallelized fault simulation but overlooked test generation. Yeh et al. in [2] demonstrate...

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Section: Introductionmentioning

confidence: 98%

Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation

Huang

Lin

et al. 2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

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show abstract

“…However, a non-deterministic parallel ATPG frequently runs into the problem of test inflation caused by race condition of multiple threads. According to [14], a 5.9% increase in pattern count can lead to a 100% increase in test cost per unit (under the worst-case scenario), not to mention the additional time and related pre-silicon effort. These aforementioned works remain suffering from test inflation; none of them can guarantee zero inflation on test pattern sets even if many of them have adopted different respective techniques to avoid repeated detection of the same faults.…”

Section: Introductionmentioning

confidence: 99%

P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings

2019

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According to the prior research, a deterministic parallel test pattern generation (TPG) engine was realized and generated the same test pattern set the serial automatic test pattern generation does during acceleration. However, for retaining the determinism, tremendous idle time is observed when different tasks (either dependent or independent) were synchronized among threads. Therefore, a new deterministic parallel TPG engine called P4-TPG is developed and incorporates preemptive, proactive, and preventive schedulings to further save/reuse the idle time during acceleration. In P4-TPG, preemptive scheduling first modifies the thread flow and brings forward, as many latter tasks as possible, to the idle time. Next, proactive scheduling inserts prospective TPG tasks of unprocessed faults to the remaining idle time and increases the overall utilization of threads. Last, preventive scheduling dynamically skips faults incompatible with the working pattern per thread and shortens the fault list during fault compaction. The experimental results show that P4-TPG not only generates the same test pattern set as the serial TPG does but also achieves averagely 10.36× speedups, is 96.6% better than the prior research, using 12 threads on 18 benchmark circuits.

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“…I. D. Dear et.al. [4] The authors discussed the economics of test. The EVEREST test strategy planner tool, wh ich is used for the test planning.…”

Section: Introductionmentioning

confidence: 99%

Cost Modeling for SOC Modules Testing

Singh¹,

Khosla²,

Narang³

2013

IJIEEB

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-The complexity of the system design is increasing very rapidly as the number of transistors on Integrated Circuits (IC) doubles as per Moore's law. There is big challenge of testing this comp lex VLSI circuit, in which whole system is integrated into a single chip called System on Ch ip (SOC). Cost of testing the SOC is also increasing with comp lexity. Cost modeling plays a vital role in reduction of test cost and time to market. This paper includes the cost modeling of the SOC Module testing which contains both analog and digital modules. The various test cost parameters and equations are considered fro m the prev ious work. The mathematical relations are developed for cost modeling to test the SOC further cost modeling equations are modeled in Graphical User Interface (GUI) in MATLA B, which can be used as a cost estimat ion tool. A case study is done to calculate the cost of the SOC testing due to Logic Built in Self Test (LBIST) and Memory Built in Self Test (MBIST). VLSI Test engineers can take the benefits of such cost estimat ion tools for test planning.

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Economic effects in design and test

Cited by 33 publications

References 15 publications

Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation

Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation

P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings

Cost Modeling for SOC Modules Testing

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