Eclipse: heterogeneous multiprocessor architecture for flexible media processing

Rutten, Martijn J.; Eijndhoven, J.T.J. van; Egbert, E.D. Pol; Jaspers, G.T.; Wolf, Pieter van der; Gangwal, Om Prakash; Timmer, A.H.

doi:10.1109/ipdps.2002.1016517

Cited by 16 publications

(13 citation statements)

References 23 publications

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“…Table 3 gives an overview of four SoC subsystem architecture templates: the MOVE project at Delft University of Technology [26], Philips Research Prophid/CPA [136], Intel MXP [72], and Philips Research Eclipse [121]. …”

Section: Soc Subsystem Architecture Templatesmentioning

confidence: 99%

Eclipse : Flexible Media Processing in a Heterogeneous Multiprocessor Template

Rutten¹

2007

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All rights reserved. Without limiting the rights under copyright reserved above, no part of this book may be reproduced, stored in or introduced into a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photocopying, recording or otherwise) without the written permission of both the copyright owner and the author of the book. Acknowledgmentith this thesis, I stand on the shoulders of two remarkable architects, Evert-Jan Pol and Jos van Eijndhoven. Ever so often, I would study a certain aspect of the architecture. Typically, when I proudly presented my solution after careful consideration of all options, Evert-Jan would politely point out to me that I had overlooked a detail that rendered my solution utterly useless. However, my ideas triggered him to change one detail and invent the final solution, letting me wonder why I couldn't have come up with that. Next, Jos van Eijndhoven would pass by as an interested onlooker and within minutes sketch a highly innovative implementation on the white board. Jos and Evert-Jan: a very special thanks for all the support, coaching, and friendship. Evert-Jan, I am extremely grateful for all the architecting experience you taught me over the many years we worked together, and particularly for helping me to reverse engineer the design decisions in the EDDI use cases after a few years. W Clearly, this thesis builds on the work of many other researchers: Egbert Jaspers and Erik van der Tol, showing me what MPEG-2 really means; Pieter van der Wolf-who was one of the first to stress that Eclipse had a value far beyond a TriMedia accelerator. Pieter, thanks for teaching me how to properly structure a document and for all the last-minute reviewing of Eclipse papers, typically a few hours before the submission deadline. Thanks to John Moors, struggling to decrypt my coprocessor shell design document during RTL implementation. Karel Walters, your enthusiasm and skill in developing the Eclipse control software was inspiring! I will never forget the enthusiasm of the Semiconductors and Research teams in India. Ferry, thanks for all the times you rescued me from spending all weekend typing on my thesis in Bangalore! My gratitude goes out to Bob Hertzberger for supporting this thesis since 2002. Jacqueline, thank you for your help and support during these years! I am deeply indebted to my parents for virtually everything, with a special thanks to my father for reviewing and kayaking with me whenever it's too cold to stay home. Last but not least, a huge thanks to Katrien, Open Office guru Andrei, Jaap, Maca, Nanni, Enith, Giuseppe, Loes, Wouter, Joep, Joost, Csaba, Thibaut, Alex, Vedran, Andreja, Mathias, Clara, and Jaques for always asking when I would finally finish my thesis and at the same time inviting me to do other fun things… viii Acknowledgment I will never have enough pages to thank you, Derya, for being so sweet despite all the time I spent behind my laptop and left you alone…tatlı karıcım, sevgin ve desteğin için çok teşekkurler!

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Section: Soc Subsystem Architecture Templatesmentioning

confidence: 99%

Eclipse : Flexible Media Processing in a Heterogeneous Multiprocessor Template

Rutten¹

2007

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“…Tensilica [27] enables rapid design of highly efficient processor cores by extending the processor hardware and software to fit each system's application requirements based on a lean core implementation. The Eclipse [24] provides an architecture template at subsystem level. It supports the reuse of design effort for providing a set of parameterized rules for subsystem composition.…”

Section: Related Workmentioning

confidence: 99%

Flexible heterogeneous multicore architectures for versatile media processing via customized long instruction words

Chen

Hsu

2005

IEEE Trans. Circuits Syst. Video Technol.

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To meet varying requirements for a wide variety of contemporary media applications with evolving standards, a generic and flexible media-processing design platform is essential to manage increasing system-on-a-chip (SoC) design complexity with minimal design cost and time-to-market. A possible solution to the problem is combining several reconfigurable hardware resources with a programmable processor into a single-chip device such that flexibility and performance can be pursued at the same time. While several innovative reconfigurable architectures have been reported in the literature, none of these architectures are poised to provide the ease of software development for sophisticated SoC-based media processing applications. In this paper, we propose a new flexible heterogeneous multicore architecture system, which comprises a main reduced-instruction set computer (RISC) processor and a reconfigurable controller along with other configurable hardware blocks such as DSP processors or intellectual property blocks (IPBs). The key idea is that the interactions of those hardware blocks are grouped together and instructions are defined to express a middle-grained parallelism among intellectual property blocks in terms of several sequences of customized long instruction words (CLIW). A CLIW ROM is reconfigurable in response to application changes. We design the instruction set architecture, called reconfigurable controller, and show the implementation details. In addition, we demonstrate the necessary software tools that are needed to generate the suitable CLIW instruction code for applications.

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“…Moreover, it is also important to extract several levels of parallelism to maximally utilize all available processor cores in the multi-core platforms. For this purpose, several architectures for task-or thread-level parallelism have been introduced in the multi-core platforms [5][6][7]. Using finegrain tasks or threads provides more flexible but requires more communication for control and data.…”

Section: Introductionmentioning

confidence: 99%

Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks

Kim

Cha

Choi

et al. 2009

2009 IEEE Workshop on Signal Processing Systems

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A multi-core platform for high-performance video applications is proposed that contains multiple RISC clusters. Each cluster, which contains up to four cores and exploits thread-level parallelism, is allocated for a function block and connected to other clusters through two communication networks: one for control transfer and the other for data transfer. As an example, several mapping results of the H.264/AVC high profile 720p decoder to the proposed platform are presented. According to the experimental results, we found that this platform is suitable for implementing a multi-standard video codec.Index Terms-Multi-core platform, RISC cluster, hardware operating system kernel, communication networks

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Eclipse: heterogeneous multiprocessor architecture for flexible media processing

Cited by 16 publications

References 23 publications

Eclipse : Flexible Media Processing in a Heterogeneous Multiprocessor Template

Eclipse : Flexible Media Processing in a Heterogeneous Multiprocessor Template

Flexible heterogeneous multicore architectures for versatile media processing via customized long instruction words

Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks

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