ECL I/O buffers for BiCMOS integrated systems: A tutorial overview

A global synchronization network for a non-deterministic simulation architecture

“…The signal propagation delay is assumed to be composed of the time required to propagate a signal through each reduction gate in the array as depicted in Figure 4. The gates are assumed to be high speed Emmiter-Coupled Logic (ECL) one nanosecond delay gates (Pickles 1997). Processing elements are assumed to be deployed along linear buses whose lengths are determined by the number of processors in the simulation.…”

A global synchronization network for a non-deterministic simulation architecture

“…Multiple transmitters share the bus and are able to generate signals simultaneously. The bus architecture is composed of a bi-directional reduction logic network employing Emitter Coupled Logic (ECL) (Pickles 1997) which gives the interface reasonable transmission speed, and ECL hardware connects nicely with CMOS technology (Chappell 1988). ECL switching speed is accomplished by keeping transistors always biased in their active regions.…”

“…At [gate] logic speeds of two nanoseconds, an equivalent gate delay is introduced by every foot of the interconnecting lines (MECL 1989). The gate delays of the proposed devices are expected to be approximately one nanosecond (Pickles 1997). The 3-dimensional cubic array network illustrated in Figure 6 keeps all interconnection lengths uniformly short.…”