ECG performance validation using operational transconductance amplifier with bias current

Vijay, Vallabhuni; Reddy, C. V. Sai Kumar; Pittala, Chandra Shaker; Vallabhuni, Rajeev Ratna; Saritha, M.; Lavanya, M.; Venkateswarlu, S. China; Sreevani, M.

doi:10.1007/s13198-021-01372-9

Cited by 28 publications

(25 citation statements)

References 17 publications

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“…Utilizing the 8-Bit Multipliers, the 16-Bit Multiplier is then developed. [13] Finally, utilizing these 16-Bit Multipliers, we have designed the proposed model and improved version of the fast 32-Bit Vedic Multiplier.…”

Section: Proposed Model Of the Improved Vedic Multipliermentioning

confidence: 99%

Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer

2023

VLSI

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This paper demonstrates the improved adaptation of the Vedic Multiplier using the Vedic standards, which includes old sutras. In this paper, current and proposed model are examined. Verilog HDL is utilized to execute the improved adaptation of Vedic Multiplier. Streamlined proposed model can likewise be utilized to achieve higher-request bits duplication exercises up to 32 bits. Vedic Multiplier up to 32-bit, the reproduction results are examined. These outcomes showed that the streamlined Vedic multiplier changed the execution improvement measurements, for example, time delay, also in device use too. Alongside this, a correlation is made among existing and enhanced proposed model to recognize about the presentation improvement measurements.

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Section: Proposed Model Of the Improved Vedic Multipliermentioning

confidence: 99%

Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer

2023

VLSI

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“…This can effectively reduce the noise of the circuit because the larger current can reduce the transmitted noise. Also, pmos is used in all OTAs for the design because pmos introduces less flicker noise compared to nmos [8]. The schematic diagram of the operational transconductance amplifier used in this design is shown in Figure 4.…”

Section: Operational Transduction Amplifier (Ota)mentioning

confidence: 99%

Design of low-noise low-power ECG amplifier circuit with high integration level

Wang

2023

J. Phys.: Conf. Ser.

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Electrocardiogram (ECG) is a common tool in medicine and is an important indicator for diagnosing many diseases. Nowadays, aspects such as low noise, low power, and high integration have become important indicators for ECG circuit design. Also, due to the low amplitude of ECG signals, ECG circuits need to have high gain to ensure accurate signal detection and analysis. Second, ECG signals are usually subject to interference from other parts of the body, so a high common mode rejection ratio (CMRR) is required to suppress these interfering signals. In this paper, we propose an ECG circuit composed of an amplifier with a drive right leg circuit (DRL) using pseudo-resistors as well as capacitors to improve the common instrumentation amplifier. The simulation using industrial-grade simulation software LTspice shows that the circuit has a voltage of 1.8 V, a bandwidth of 17 mHz-1 KHz, a gain of 55 dB, and an INR of 3.4 μVrms, and because the signal amplifier part of this circuit design consists of only pseudo-pseudo-resistors, capacitors, and mos tubes. Therefore, it has a smaller size and a higher degree of integration. In addition, the circuit has less power loss for the same amplification design. Overall, this design has excellent characteristics such as low noise, low power, and small size.

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“…It happens because the source and drain terminals of the MOSFET become to be closer. [14][15][16][17][18][19][20][21] As a result of that, the gate terminal of the MOSFET starts to lose the control of the channel. Those undesirable effects which causes negative behaviour of transistor are called "short-channel effects" (SCE).…”

Section: Finfet Characteristics and Modellingmentioning

confidence: 99%

“…[3] Due to this property, it is popularly used for data error correction and detection in digital communication. [16][17][18][19][20][21] We know that the barrel shifter block plays a vital role in performance of the device from last chapter. Due to its importance, several studies were made by researchers to improve its performance for increasing its applications.…”

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confidence: 99%

Data Conversion: Realization of Code converter using Shift Register Modules

2023

VLSI

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Barrel shifter architecture is well known for bit manipulation in a single clock cycle. Due to its various operations and advantages, it is most likely used in the Arithmetic logic unit of every processor. Gray code is also known as reflective code which is widely used in digital communication for the purpose of error correction and error detection. In this project, an 8 x 4 barrel shifter is designed which is further connected to 4-bit binary to gray code converter. The barrel shifter is cascaded with binary to gray code converter so that this combination can be useful for the application of encryption of binary data in digital communications. It is designed in cadence virtuoso tool using FinFET technology at 18 nm node. The simulation results proves that the power consumed by the proposed design with FinFET technology is 11.92% less when compared with the conventional design with MOS transistors. Hence, this design can be used in application of low power digital communications. The functionality testing and verification is done using cadence virtuoso tool.

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ECG performance validation using operational transconductance amplifier with bias current

Cited by 28 publications

References 17 publications

Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer

Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer

Design of low-noise low-power ECG amplifier circuit with high integration level

Data Conversion: Realization of Code converter using Shift Register Modules

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