Early results from ERA &amp;#x2014; Embedded Reconfigurable Architectures

Wong, Stephan; Brandon, Anthony; Anjam, Fakhar; Seedorf, Roel; Giorgi, Roberto; Yu, Zhibin; Puzovic, Nikola; McKee, Sally A.; Själander, Magnus; Carro, Luigi; Κεραμίδας, Γεώργιος

doi:10.1109/indin.2011.6034998

Cited by 7 publications

(3 citation statements)

References 8 publications

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“…The embedded systems community is continuously seeking for low power consumption and high performance applications (Wong et al, 2011;Portilla et al, 2007;Ho et al, 2006).…”

Section: Related Workmentioning

confidence: 99%

An analysis on power consumption and performance in runtime hardware reconfiguration

Loubach¹

2021

IJES

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It will be more difficult to continue with Moore's law scaling in the next years without exploring new heterogeneous architectures with application-customised hardware. The expressive employment of customised accelerators, or runtime reconfigurable designs, will be required to deliver power-and performance-efficient systems. In view of recent technology advances, runtime partial reconfiguration has emerged supported by FPGA-based devices. Still, power consumption and performance are the principal concerns when devising new reconfigurable embedded systems. This paper addresses power and performance analysis of the partial reconfiguration process supported by runtime reconfigurable hardware. We introduce a heterogeneous system-on-chip FPGA-based runtime partial reconfigurable platform design along with an experimental and theoretical power consumption and performance models, which are specific to the partial reconfiguration process. The proposed design was implemented, and both experimental and theoretical power consumption and performance analyses were performed, thus providing a formal tool to the decision-making process between power consumption and performance applicable to the runtime reconfiguration phase. Results show an average accuracy of 89.76% for the power consumption model and 94.82% for the performance model.

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“…The embedded systems community is continuously seeking for low power consumption and high performance applications (Wong et al, 2011;Portilla et al, 2007;Ho et al, 2006).…”

Section: Related Workmentioning

confidence: 99%

An analysis on power consumption and performance in runtime hardware reconfiguration

Loubach¹

2021

IJES

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“…The ERA project [5] focuses on developing a platform consisting of reconfigurable very large instruction word processors on field programmable gate arrays (FPGA). Those processors are connected through a network on chip to memory subsystems.…”

Section: Related Workmentioning

confidence: 99%

A new concept for system-level design of runtime reconfigurable real-time systems

Luppold¹,

Menhorn²,

Falk³

et al. 2013

SIGBED Rev.

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This concept paper proposes a new system-level design methodology for runtime reconfigurable adaptive heterogeneous systems in a real-time environment. Today, among those approaches dealing with runtime reconfiguration and hardware/software co-design, compliance with hard real-time conditions is not guaranteed. Our approach will fill this gap. In contrast to other approaches, we apply methods of real-time analysis to embedded reconfigurable systems. An extended compiler and a runtime resource manager guarantee both synthesis and reconfiguration in a (hard) real-time environment. With this approach, the system can adapt to changes in requirements and operational environments during runtime.

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“…ere are parameters which make simulators preferable to reach a certain level of performance, scalability, and accuracy as well as reproducibility and observability. Based on the experience of previous projects such as TERAFLUX [6,7], ERA [8,9], AXIOM [4, [10][11][12][13], and SARC [14,15], we choose to rely on the HP-Labs COTSon simulation infrastructure [16]. e key feature of COTSon that is useful in HLS design is its "functional-directed" approach, which separates the functional simulation from the timing one.…”

Section: Introductionmentioning

confidence: 99%

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

Giorgi

Khalili

Procaccini

2019

International Journal of Reconfigurable Computing

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Translating a system requirement into a low-level representation (e.g., register transfer level or RTL) is the typical goal of the design of FPGA-based systems. However, the Design Space Exploration (DSE) needed to identify the final architecture may be time consuming, even when using high-level synthesis (HLS) tools. In this article, we illustrate our hybrid methodology, which uses a frontend for HLS so that the DSE is performed more rapidly by using a higher level abstraction, but without losing accuracy, thanks to the HP-Labs COTSon simulation infrastructure in combination with our DSE tools (MYDSE tools). In particular, this proposed methodology proved useful to achieve an appropriate design of a whole system in a shorter time than trying to design everything directly in HLS. Our motivating problem was to deploy a novel execution model called data-flow threads (DF-Threads) running on yet-to-be-designed hardware. For that goal, directly using the HLS was too premature in the design cycle. Therefore, a key point of our methodology consists in defining the first prototype in our simulation framework and gradually migrating the design into the Xilinx HLS after validating the key performance metrics of our novel system in the simulator. To explain this workflow, we first use a simple driving example consisting in the modelling of a two-way associative cache. Then, we explain how we generalized this methodology and describe the types of results that we were able to analyze in the AXIOM project, which helped us reduce the development time from months/weeks to days/hours.

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Early results from ERA — Embedded Reconfigurable Architectures

Cited by 7 publications

References 8 publications

An analysis on power consumption and performance in runtime hardware reconfiguration

An analysis on power consumption and performance in runtime hardware reconfiguration

A new concept for system-level design of runtime reconfigurable real-time systems

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

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