Early load address resolution via register tracking

Abstract

Higher microprocessor frequencies accentuate the performance cost of memory accesses. This is especially noticeable in the Intel's IA32 architecture where lack of registers results in increased number of memory accesses. This paper presents novel, non-speculative technique that partially hides the increasing loadto-use latency, by allowing the early issue of load instructions. Early load address resolution relies on register tracking to safely compute the addresses of memory references in the front-end part of the processor pipeline. Register tracking enables decode-time computation of register values by tracking simple operations of the form reg±immediate. Register tracking may be performed in any pipeline stage following instruction decode and prior to execution. Several tracking schemes are proposed in this paper: • Stack pointer tracking allows safe early resolution of stack references by keeping track of the value of the ESP register (the stack pointer). About 25% of all loads are stack loads and 95% of these loads may be resolved in the front-end. • Absolute address tracking allows the early resolution of constant-address loads. • Displacement-based tracking tackles all loads with addresses of the form reg±immediate by tracking the values of all general-purpose registers. This class corresponds to 82% of all loads, and about 65% of these loads can be safely resolved in the front-end pipeline. The paper describes the tracking schemes, analyzes their performance potential in a deeply pipelined processor and discusses the integration of tracking with memory disambiguation.

RENO: a rename-based instruction optimizer

“…Register tracking [2] uses the rename stage to fold stack-pointer-immediate additions and create a fast, speculative address-generation and issue path for stack loads. Unlike RENO, register tracking does not optimize the main instruction stream inline.…”

Performance Potential of Effective Address Prediction of Load Instructions

“…Austin and Sohi [14] proposed overlapping effective address computation with cache access with the help of special circuits and software support. Bekerman, et al [6] proposed tracking certain registers and immediate values to calculate a load's effective address earlier in the pipeline. We believe that a combination of these techniques along with the effective address predictors we studied in this paper will lead to good effective address prediction rates.…”

L1 data cache decomposition for energy efficiency

“…Consequently, we need to detect stack references. A good way to do so has been proposed by Bekerman et al [3]. In the decode stage, instructions that use the stack pointer are identified.…”

“…With this solution, only the accesses redirected by the snooping mechanism to the SSC require one additional cycle. According to [3], only 1.2% of the accesses need any redirection.…”