Early evaluation for performance enhancement in phased logic

Reese, R.B.; Thornton, Mitchell A.; Traver, C.; Hemmendinger, David

doi:10.1109/tcad.2005.844084

Cited by 16 publications

(15 citation statements)

References 21 publications

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“…It is a more practical restriction of the OR-causality precedence relation for which Yakovlev et al provide formal models and implementations for speed-independent asynchronous circuits in [26] and [27]. Early evaluation has been applied to phased logic at different granularity levels by Reese et al [28], [29] and to the optimization of pipelined asynchronous logic by both Brej and Garside [30] and, more recently, by Ampalam and Singh [31].…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip

Carloni

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Latency-insensitive design is a methodology for system-on-chip (SoC) design that simplifies the reuse of intellectual property cores and the implementation of the communication among them. This simplification is based on a system-level protocol that decouples the intracore logic design from the design of the intercore communication channels. Each core is encapsulated within a shell, a synthesized logic block that dynamically controls its operation to interface it with the rest of the SoC and absorb any latency variations on its I/O signals. In particular, a shell stalls a core whenever new valid data are not available on the input channels or a downlink core has requested a delay in the data production on the output channels. We study how knowledge about the internal logic structure of a core can be applied to the design of its shell to improve the overall system-level performance by avoiding unnecessary local stalling. We introduce the notion of functional independence condition (FIC) and present a novel circuit design of a generic shell template that can leverage FIC. We propose a procedure for the logic synthesis of a FIC-shell instance that is only based on the analysis of the intracore logic and does not require any input from the designers. Finally, we present a comprehensive experimental analysis that shows the performance benefits and limited design overhead of the proposed technique. This includes the semicustom design of an SoC, an ultrawideband baseband transmitter, using a 90-nm industrial standard cell library.Index Terms-Finite state machines (FSMs), latency-insensitive design (LID), logic synthesis, sequential logic optimization, system-level design, system-on-chip (SoCs).

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Section: Related Workmentioning

confidence: 99%

“…The idea is to withhold the acknowledgement until all data arrive, even if some early arrivals already trigger the computation. Reese et al [28], [29] use Petri nets to model and implement such a handshaking mechanism for asynchronous phased-logic systems.…”

Section: ) Detection Logicmentioning

confidence: 99%

Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip

Carloni

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Therefore, the result a = 0 could be produced by an early evaluation of the expression. Early evaluation has been proposed and used in asynchronous design [41,42]. Usual Petri nets are not capable of modeling early evaluation, since the enabling of transitions is based on AND-causality, i.e., all input conditions must be asserted.…”

Section: Motivation and Examplesmentioning

confidence: 99%

Elasticity and Petri Nets

Cortadella

Kishinevsky

Bufistov

et al. 2008

Transactions on Petri Nets and Other Models of Concurrency I

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Abstract. Digital electronic systems typically use synchronous clocks and primarily assume fixed duration of their operations to simplify the design process. Time elastic systems can be constructed either by replacing the clock with communication handshakes (asynchronous version) or by augmenting the clock with a synchronous version of a handshake (synchronous version). Time elastic systems can tolerate static and dynamic changes in delays (asynchronous case) or latencies (synchronous case) of operations that can be used for modularity, ease of reuse and better power-delay trade-off. This paper describes methods for the modeling, performance analysis and optimization of elastic systems using Marked Graphs and their extensions capable of describing behavior with early evaluation. The paper uses synchronous elastic systems (aka latency-tolerant systems) for illustrating the use of Petri Nets, however most of the methods can be applied without changes (except changing the delay model associated with events of the system) to asynchronous elastic systems.

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“…In that case, the result z = a can be produced and the value of b can be discarded when it arrives at the multiplexor. Early evaluation has been proposed and used in asynchronous design [2,10].…”

Section: Early Evaluationmentioning

confidence: 99%

Performance analysis of concurrent systems with early evaluation

Jülvez

Cortadella

Kishinevsky

2006

2006 IEEE/ACM International Conference on Computer Aided Design

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Early evaluation allows to execute operations when enough information at the inputs has been received to determine the value at the outputs. Systems that can tolerate variable-latency units, such as latency-insensitive or asynchronous systems, can enhance their performance by using early evaluation. The most relevant example of a unit with early evaluation is the multiplexor: the output can be determined as soon as the information of the selected channel arrives, without waiting for the other channels. This paper analyzes the potential impact of early evaluation in concurrent systems. An analytical model, based on a Petri net extension with early firing is proposed to estimate the performance. The reduction of the analytical model to a linear programming formulation for an efficient estimation of the upper bound for the system throughput is proposed. The results show the accuracy of the model and the benefits of early evaluation.

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Early evaluation for performance enhancement in phased logic

Cited by 16 publications

References 21 publications

Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip

Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip

Elasticity and Petri Nets

Performance analysis of concurrent systems with early evaluation

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