Early detection of successful decoding for dual-diagonal block-based LDPC codes

Abstract

A fast, successful decoding detection mechanism is proposed for dualdiagonal block-based low-density parity-check (LDPC) codes. The algorithm eliminates unnecessary parity check computation by exploiting the structure of dual-diagonal LDPC codes. The average number of decoding iterations can be reduced for both two-phase decoders and layered decoders with no performance degradation on the AWGN channel. Simulation results show that the proposed mechanism reduces average iterations by 10-15% at 10 25 bit error rate compared with standard parity-check equations.

Forced-convergence decoding for LDPC-coded modulation

“…Both the demapping and decoding account for a great proportion of the overall receiver complexity. There have been many methods proposed for reducing the complexity of LDPC decoding [10][11][12][13][14][15][16][17][18]. The forced-convergence (FC) decoding of LDPC code [14][15][16][17][18] is one type, and it significantly reduces the decoding complexity by deactivating or deleting the converged nodes identified in early iterations.…”

“…Figure 8 describes the average computational complexity per information bit for the three decoding algorithms using Eqs. (11)- (13). The figure shows that, compared with conventional BP decoding, the proposed scheme greatly reduces the computational complexity by 64% at E b N0 = 2.4 dB, and by 58% at…”

“…The reductions are 28% and 17% respectively relative to FC decoding. The reductions can be explained in that d j (i) c < d j c and N it has a minimum value in (13). Figure 9 illustrates the average logical complexity per information bit.…”