DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing

Govindaraju, Venkatraman; Ho, Chen-Han; Nowatzki, Tony; Chhugani, Jatin; Satish, Nadathur; Sankaralingam, Karthikeyan; Kim, Changkyu

doi:10.1109/mm.2012.51

Cited by 205 publications

(98 citation statements)

References 13 publications

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“…Hardware acceleration exists in many forms, such as analog accelerators [6,50], static [13,19,28,38,43,52,55] and dynamic datapath accelerators [14,25,27], and programmable accelerators, such as GPUs and DSPs. In this work, we focus on static datapath accelerators.…”

Section: Background and Motivationmentioning

confidence: 99%

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Shao¹,

Reagen²,

Wei³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

118

117

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Hardware specialization, in the form of accelerators that provide custom datapath and control for specific algorithms and applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in accelerator analysis relies on RTL-based synthesis flows to produce accurate timing, power, and area estimates. Such techniques not only require significant effort and expertise but are also slow and tedious to use, making large design space exploration infeasible. To overcome this problem, we present Aladdin, a pre-RTL, power-performance accelerator modeling framework and demonstrate its application to system-on-chip (SoC) simulation. Aladdin estimates performance, power, and area of accelerators within 0.9%, 4.9%, and 6.6% with respect to RTL implementations. Integrated with architecture-level core and memory hierarchy simulators, Aladdin provides researchers an approach to model the power and performance of accelerators in an SoC environment.

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Section: Background and Motivationmentioning

confidence: 99%

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Shao¹,

Reagen²,

Wei³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

118

117

View full text Add to dashboard Cite

show abstract

“…2) DySER Architecture: DySER [39], [40] was designed as a heterogeneous array of 64 functional units interconnected with a programmable network. The DySER RTL was integrated with the OpenSPARC T1 RTL and synthesized to ASIC, demonstrating a reduction in energy consumption of up to 70% and a speedup in application execution of up to 10×.…”

Section: B Spatially-configured Overlaysmentioning

confidence: 99%

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?

Jain

Maskell

Fahmy

2016

2016 IEEE 14th Intl Conf on Dependable, Autonomic and Secure Computing, 14th Intl Conf on Pervasive Intelligence and Computing,

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“…• DySER data-parallel workloads since they produce large blocks and complete code from compiler [25].…”

Section: Benchmarksmentioning

confidence: 99%

“…The fundamental insight of many specialization techniques is to "map" large regions of computation to the hardware, breaking away from instruction-byinstruction pipelined execution and instead adopting a spatial architecture paradigm. Pioneering examples include RAW [50], Wavescalar [46] and TRIPS [9], motivated primarily by performance, and recent energy-focused proposals include Tartan [39], CCA [10], PLUG [13,35], FlexCore [47], SoftHV [15], MESCAL [31], SPL [51], C-Cores [48], DySER [25,26], BERET [27], and NPU [20]. A fundamental problem in all spatial architectures is the 1 Majority of work completed while author was a PhD student at UT-Austin Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

Section: Introductionmentioning

confidence: 99%

A general constraint-centric scheduling framework for spatial architectures

Nowatzki

Sartin-Tarm

Carli

et al. 2013

Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation

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Specialized execution using spatial architectures provides energy efficient computation, but requires effective algorithms for spatially scheduling the computation. Generally, this has been solved with architecture-specific heuristics, an approach which suffers from poor compiler/architect productivity, lack of insight on optimality, and inhibits migration of techniques between architectures.Our goal is to develop a scheduling framework usable for all spatial architectures. To this end, we expresses spatial scheduling as a constraint satisfaction problem using Integer Linear Programming (ILP). We observe that architecture primitives and scheduler responsibilities can be related through five abstractions: placement of computation, routing of data, managing event timing, managing resource utilization, and forming the optimization objectives. We encode these responsibilities as 20 general ILP constraints, which are used to create schedulers for the disparate TRIPS, DySER, and PLUG architectures. Our results show that a general declarative approach using ILP is implementable, practical, and typically matches or outperforms specialized schedulers.

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DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing

Cited by 205 publications

References 13 publications

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?

A general constraint-centric scheduling framework for spatial architectures

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