DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment

Abstract

Abstract-This paper presents DynOR, a 32-bit 6-stage Open-RISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction types currently in flight in the pipeline. To this end, we employ a custom designed clock generation unit, capable of immediate glitch-free adjustments of the clock period over a wide range with fine granularity. Our chip measurements in 28 nm FD-SOI technology show that DynOR provides an average speedup of 19% in program execution over a wide range of operating conditions, with a peak speedup for certain applications of up to 41%. Furthermore, this speedup can be traded off against energy, to reduce the chip power consumption for a typical die by up to 15%, compared to a static clocking scheme based on worst case excitation. I. INTRODUCTIONThe concept of dynamic voltage frequency scaling (DVFS) has been one of the leading approaches to energy-efficient operation for the past twenty years. Furthermore, the introduction of in-situ error-detection, such as Razor [4], [5], and tunable replica circuits with error-detection [6] led to an influx of designs targeted at real-time adjustment for voltage overscaling or over-clocking, according to detected errors [7], [8]. While these innovations have succeeded in pushing margin reduction to the limit, they rely on the capability of the microarchitecture to correct a limited number of errors, for example by replay of instructions.Despite the impressive results and innovative techniques proposed in these and other recent publications, they all adhere to the basic assumption that the clock period must be set according to a global worst-case timing path. However, the study carried out in [9] showed that by applying a nonconventional synthesis strategy to a standard microprocessor core, the longest relevant path for a given pipeline state can vary significantly, depending on the executed instruction types. Therefore, by departing from the conventional global frequency convention and adjusting the clock frequency according to the current pipeline state, margins can be reduced and average throughput and/or energy-efficiency can be improved. In this paper, we present DynOR, a full operational circuit implementing this novel approach, designed and fabricated in a deeply-scaled 28 nm fully-depleted silicon-on-insulator (FD-SOI) technology.Contributions and Outline: The specific contributions of this work are: 1) A dynamic clock adjustment (DCA) technique and corresponding micro-architecture, which enables the trimming of dynamic timing margins occurring in a microprocessor, which results in an increased instruction throughput.2) The first silicon implementation of a microprocessor oper-

Frequency Scaling for High Performance of Low-End Pipelined Processors

“…This approach utilizes a phase generator which can modify the clock's phase in order to stretch its period. Similarly, in [21] authors employ a dynamic clock adjustment technique on a simple processor pipeline to adjust the clock frequency according to the application type that is being executed www.astesj.com 764 on the processor pipeline. TS designs are often prone to exhibit metastable behavior, resulting in non-deterministic timing phenomena which should be taken into account when designing a TS processor [5], [22].…”

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI

“…(c) Fast-path measurement (FPM). and it can enable adaptive dynamic voltage and frequency scaling, whenever the critical path is not excited [9], [10].…”

“…Nevertheless, as the critical path of a design is not always excited, the activated paths might have a significantly shorter delay compared to the critical path, depending for example on the instruction executed by a microprocessor core [9]. For this reason, the available timing-slack needs to be measured for a wide detection-window, so these timing margins can be exploited by either increasing the operating frequency or by applying dynamic voltage scaling at run-time depending on the instruction executed in the core [10].…”

“…In addition, by adjusting the low phase of the clock in BDM, the TMS can measure the timing slack of paths that are far from being critical. This capability can provide insightful information to either exploit the available timing margins [9], [10] or for offline diagnostics. Results from postlayout simulations are provided to evaluate the performance of the TMS, and both FDM and BDM are verified with measurements from a test chip fabricated in 28 nm FD-SOI process technology, which included a 16-bit digital multiplier, implemented with TMS cells.…”

Modelagem, simulação e caracterização elétrica da associação série assimétrica de transistores SOI

“…Dentre as vantagens da tecnologia SOI em relação à tecnologia bulk, pode-se citar a eliminação do efeito tiristor parasitário, a redução das capacitâncias de fonte e dreno, a facilidade de fabricação de junções rasas, a resistência à radiação e a operação em altas temperaturas (COLINGE, 2004). 36 Atualmente, a tecnologia SOI está presente nos mais diversos circuitos integrados de alta densidade e complexidade, tais como microprocessadores (CONSTANTIN et al, 2016;ZYUBAN et al, 2015), memórias (CAI et al, 2017;KOSSEL et al, 2013), amplificadores (CHEN et al, 2013;HELMI;MOHAMMADI, 2016), entre outras aplicações.…”