Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses

Vogelstein, R. Jacob; Mallik, Udayan; Vogelstein, Joshua T.; Cauwenberghs, Gert

doi:10.1109/tnn.2006.883007

Cited by 207 publications

(139 citation statements)

References 58 publications

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“…In this prototype the visual processing (visual stimulus orientation detection) was performed by real-time address-event processing software (57). In future versions this processing could also be performed in neuromorphic hardware by using simple-cell orientation selectivity hardware models (58,59) or event-driven convolution chips (60).…”

Section: Discussionmentioning

confidence: 99%

Synthesizing cognition in neuromorphic electronic systems

Neftci

Binas

Rutishauser

et al. 2013

Proc. Natl. Acad. Sci. U.S.A.

124

119

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The quest to implement intelligent processing in electronic neuromorphic systems lacks methods for achieving reliable behavioral dynamics on substrates of inherently imprecise and noisy neurons. Here we report a solution to this problem that involves first mapping an unreliable hardware layer of spiking silicon neurons into an abstract computational layer composed of generic reliable subnetworks of model neurons and then composing the target behavioral dynamics as a "soft state machine" running on these reliable subnets. In the first step, the neural networks of the abstract layer are realized on the hardware substrate by mapping the neuron circuit bias voltages to the model parameters. This mapping is obtained by an automatic method in which the electronic circuit biases are calibrated against the model parameters by a series of population activity measurements. The abstract computational layer is formed by configuring neural networks as generic soft winner-take-all subnetworks that provide reliable processing by virtue of their active gain, signal restoration, and multistability. The necessary states and transitions of the desired high-level behavior are then easily embedded in the computational layer by introducing only sparse connections between some neurons of the various subnets. We demonstrate this synthesis method for a neuromorphic sensory agent that performs real-time context-dependent classification of motion patterns observed by a silicon retina.decision making | sensorimotor | working memory | analog very large-scale integration | artificial neural systems U nlike digital simulations, in which the dynamics of neuronal models are encoded and calculated on general purpose digital hardware, "neuromorphic" emulations express the dynamics of the neural systems directly on an analogous physical substrate (1). Digital simulations have the advantage that they can be exactly and reliably programmed using numerical operations of very high precision. However, they suffer the disadvantage that they are cast on abstract binary electronic circuits whose operation is entirely divorced from the physical processes being simulated. Consequently, such simulations do not readily advance our understanding of how biological neural systems are able to attain their extraordinary physical performance, using only large numbers of apparently unreliable, slow, and imprecise neural components, a problem first recognized by von Neumann more than a half century ago (2). Furthermore, the reliability of digital systems comes at high cost of the circuit complexity necessary for the orchestration of communication and processing, an overhead that declares itself also in the costs of system construction and power dissipation (3).The alternative, neuromorphic, approach to information processing strives to capture in complementary metal-oxide semiconductor (CMOS) very large-scale integration (VLSI) electronic technology the more distributed, asynchronous, and limited precision nature of biological intelligent systems (1, 4).†, ‡ Research...

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Section: Discussionmentioning

confidence: 99%

Synthesizing cognition in neuromorphic electronic systems

Neftci

Binas

Rutishauser

et al. 2013

Proc. Natl. Acad. Sci. U.S.A.

124

119

View full text Add to dashboard Cite

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“…Attempts began as early as the late 1980's [9,14]. This approach yields the greatest scope for architectural diversity as well as performance: different designs have used analogue [19] or digital [59] technology, hardwired [4] or configurable [57] architecture, continuousactivation [31] or spiking [43] signalling, coarse- [54] or fine-grained [8] parallelism. In recent years, however, interest has moved primarily towards processors for the simulation of spiking neural networks.…”

Section: Dedicated Neural Hardwarementioning

confidence: 99%

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

Rast

Navaridas

Jin

et al. 2011

Int J Parallel Prog

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Neural networks present a fundamentally different model of computation from the conventional sequential digital model, for which conventional hardware is typically poorly matched. However, a combination of model and scalability limitations has meant that neither dedicated neural chips nor FPGA's have offered an entirely satisfactory solution. SpiNNaker introduces a different approach, the "neuromimetic" architecture, that maintains the neural optimisation of dedicated chips while offering FPGA-like universal configurability. This parallel multiprocessor employs an asynchronous event-driven model that uses interrupt-generating dedicated hardware on the chip to support real-time neural simulation. Nonetheless, event handling, particularly packet servicing, requires careful and innovative design in order to avoid local processor congestion and possible deadlock. We explore the impact that spatial locality, temporal causality and burstiness of traffic have on network performance, using tunable, biologically similar synthetic traffic patterns. Having established the viability of the system for real-time operation, we use two exemplar neural models to illustrate how to implement efficient event-handling service routines that mitigate the problem of burstiness in the traffic. Extending work published in ACM Computing Frontiers 2010 with on-chip testing, simulation results indicate the viability of SpiNNaker for large-scale neural modelling, while emphasizing the need for effective burst management and network mapping. Ultimately, the goal is the creation of a library-based development system that can translate a high-level neural model from any description 123Int J Parallel Prog environment into an efficient SpiNNaker instantiation. The complete system represents a general-purpose platform that can generate an arbitrary neural network and run it with hardware speed and scale.

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“…Spiking networks make it possible to abstract the signalling to a zero-time point process, and this forms the basis of the emerging neural data serialisation standard: AddressEvent Representation (AER) [18]. AER uses packets that encode the source of the spike as an address and is a proven, efficient way to serialise and then multiplex multiple neural signals onto the same series of lines [19] while making the converters themselves trivial [20]. AER is well established on the way to becoming a defined standard [1], thus making it overwhelmingly the signalling method of choice for future neural designs.…”

Section: Neuromorphic Hardwarementioning

confidence: 99%

An event-driven model for the SpiNNaker virtual synaptic channel

Rast

Galluppi

Davies

et al. 2011

The 2011 International Joint Conference on Neural Networks

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Abstract-Neural networks present a fundamentally different model of computation from conventional sequential hardware, making it inefficient for very-large-scale models. Current neuromorphic devices do not yet offer a fully satisfactory solution even though they have improved simulation performance, in part because of fixed hardware, in part because of poor software support. SpiNNaker introduces a different approach, the "neuromimetic" architecture, that maintains the neural optimisation of dedicated chips while offering FPGA-like universal configurability. Central to this parallel multiprocessor is an asynchronous event-driven model that uses interruptgenerating dedicated hardware on the chip to support realtime neural simulation. In turn this requires an event-driven software model: a rethink as fundamental as that of the hardware. We examine this event-driven software model for an important hardware subsystem, the previously-introduced virtual synaptic channel. Using a scheduler-based system service architecture, the software can "hide" low-level processes and events from models so that the only event the model sees is "spike received". Results from simulation on-chip demonstrate the robustness of the system even in the presence of extremely bursty, unpredictable traffic, but also expose important modellevel tradeoffs that are a consequence of the physical nature of the SpiNNaker chip. This event-driven subsystem is the first component of a library-based development system that allows the user to describe a model in a high-level neural description environment and be able to rely on a lower layer of system services to execute the model efficiently on SpiNNaker. Such a system realises a general-purpose platform that can generate an arbitrary neural network and run it with hardware speed and scale.

show abstract

Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses

Cited by 207 publications

References 58 publications

Synthesizing cognition in neuromorphic electronic systems

Synthesizing cognition in neuromorphic electronic systems

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

An event-driven model for the SpiNNaker virtual synaptic channel

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