Proceedings 2017 Network and Distributed System Security Symposium 2017
DOI: 10.14722/ndss.2017.23024
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Dynamic Virtual Address Range Adjustment for Intra-Level Privilege Separation on ARM

Abstract: Privilege separation has long been considered as a fundamental principle in software design to mitigate the potential damage of a security attack. Much effort has been given to develop various privilege separation schemes where a monolithic OS or hypervisor is divided into two privilege domains where one domain is logically more privileged than the other even if both run at an identical processor privilege level. We say that privilege separation is intra-level if it is implemented for software of a certain pri… Show more

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Cited by 9 publications
(3 citation statements)
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“…Not many studies focus on this approach due to less security provided. Related techniques proposed to enhance isolation for virtualization in ARM platforms [20,21]. Inter-privilege isolation: there are couple of techniques proposed to deploy isolation environment using ARM platform [22,23].…”
Section: Software-based Teementioning
confidence: 99%
“…Not many studies focus on this approach due to less security provided. Related techniques proposed to enhance isolation for virtualization in ARM platforms [20,21]. Inter-privilege isolation: there are couple of techniques proposed to deploy isolation environment using ARM platform [22,23].…”
Section: Software-based Teementioning
confidence: 99%
“…In general, address space separation using shadow page table is widely used, but significant overhead is inevitable due to the memory management unit (MMU) configurations and TLB maintenance [29]. In some research [34], [69], the overhead of context switching between a normal kernel execution environment and a trusted kernel execution environment is reduced by reserving an ASID for the trusted kernel execution environment. Unlike the previous research, however, we considered ASID management for trusted applications.…”
Section: Kernel Deprivilegingmentioning
confidence: 99%
“…For the entry gate, in SKEE [34], the authors suggested two solutions: 1) setting the kernel and secure kernel to use different translation table base registers (TTBR0 and TTBR1) respectively, and 2) using a zero register to update the TTBR register. In addition, Hilps [69] adjusted the virtual address range by updating a control register called the translation control register (TCR) at the entry and exit gates. In this case, the gates need to check whether the control register value is valid immediately after updating the register.…”
Section: )mentioning
confidence: 99%