Dynamic Variable Ordering for Ordered Binary Decision Diagrams

Abstract-Synthesis of reversible circuits is an important research area providing the basis for a design flow of this emerging technology. Recently, in the development of scalable synthesis approaches a significant step forward has been made by a hierarchical method in combination with Shannon decomposition. However, this approach leads to circuits with high costs. In this paper, we propose an alternative that additionally makes use of positive Davio and negative Davio decomposition. We show that the usage of these decomposition types offers several advantages for the synthesis of reversible circuits. Using the proposed approach, on average the number of lines can be reduced by 22%, the number of gates by 22%, and the quantum cost by 32%. In the best case, even reductions of more than 60% are possible.

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“…Standard optimization techniques (e.g. sifting [28]) have been thereby utilized. Benchmarks from the LGSynth package have been used.…”

Section: Experimental Evaluationmentioning

confidence: 99%

Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition

Soeken

Wille

Drechsler

2010

2010 5th International Design and Test Workshop

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“…BACKGROUND has been constructed [36,37,38]. A later heuristic, based on variable sifting, was developed by Rudell [39]. In the sifting algorithm, each variable is moved up and down to greedily find its best location.…”

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confidence: 99%

“…The reordering techniques of any typical package are applied once by an explicit function call, or they can be evoked dynamically [39] by an implicit function call triggered by some memory consumption criteria. In many applications such asynchronous re-ordering has a profound effect on the resources consumed during the manipulation of BDDs.…”

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confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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KTH School of Information andCommunication Technology SE-164 40 Kista SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektronik fredagen den 26 januari 2007 klockan 9.00 i Sal E, Forumhuset, Kungl Tekniska högskolan, Isafjordsgatan 39, Kista. © Petra Färm, januari 2007Tryck: Universitetsservice US AB iii Abstract A conventional logic synthesis flow is composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions.We present a global optimization approach combining technology independent optimization steps with technology dependent objectives in an annealing-based framework. We prove that, for the presented move set and selection distribution, detailed balance is satisfied and thus the annealing process asymptotically converges to an optimal solution. Furthermore, we show that the presented approach can smoothly trade-off complex, multiple-dimensional objective functions and achieve competitive results. The combination of technology independent and technology dependent objectives is handled through dynamic weighting. Dynamic weighting reflects the sensitivity of the local graph structures with respect to the actual technology parameters such as gate sizes, delays, and power levels. The results show that, on average, the presented advanced annealing approach can improve the area and delay of circuits optimized using the Boolean optimization technique provided by SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework can be applied to two emerging technologies, chemically assembled nanotechnology and molecule cascades. New technologies are emerging because a number of physical and economic factors threaten the continued scaling of CMOS devices. Alternatives to silicon VLSI have been proposed, including techniques based on molecular electronics, quantum mechanics, and biological processes. We are hoping that our research in how to apply our developed logic synthesis framework to two of the emerging technologies might provide useful information for other designers moving in this direction.iv

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“…Heuristic BDD minimization is done by thumb rules to reorder the Boolean variables, e.g. [11]. The results are often far away from the optimum.…”

Section: Resultsmentioning

confidence: 99%

“…This is obtained while the degradation of solution quality is provably bounded and stays below a few percents on average. Equation (11) holds by Equation (9). Since q i+1 is traversed via q i on an optimal path, g(q i+1 ) = k(q i , q i+1 ) + g(q i ).…”

Section: Discussionmentioning

confidence: 99%

A Framework for Quasi-exact Optimization Using Relaxed Best-First Search

Ebendt

Drechsler

Lecture Notes in Computer Science

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Abstract. In this paper, a framework for previous and new quasi-exact extensions of the A * -algorithm is presented. In contrast to previous approaches, the new methods guarantee to expand every state at most once if guided by a socalled monotone heuristic. By that, they account more effectively for aspects of run time while still guaranteeing that the cost of the solution will not exceed the optimal cost by a certain factor. First a general upper bound for this factor is derived. This bound iswhere N is (an upper bound on) the maximum depth of the search. Next, we look at specific instances of the algorithm class described by our framework. For one of the new methods a linear, i.e. much tighter upper bound is obtained: the cost of the solution will not exceed the optimal cost by a factor greater than 1 + . The parameter ≥ 0 can be chosen by the user. Within a range of reasonable choices for , all new methods allow the user to trade off run time for solution quality. Besides that, the formal framework also serves for a comparison in terms of other algorithmic properties of interest, e.g. in terms of a necessary condition for state expansion. The results of experiments targeting the minimization of Binary Decision Diagrams (BDDs) demonstrate large reductions in run time when compared to the best known exact approach for BDD minimization and to previous relaxation methods. Moreover, the quality of the obtained solutions is often much better than the quality guaranteed by the theory.

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Dynamic Variable Ordering for Ordered Binary Decision Diagrams

Cited by 223 publications

References 2 publications

Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition

Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition

Integrated logic synthesis using simulated annealing

A Framework for Quasi-exact Optimization Using Relaxed Best-First Search

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