Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory

J. Comput. Sci. Technol.

Ota

et al. 2011

We consider the energy saving problem for caches on a multi-core processor. In the previous research on low power processors, there are various methods to reduce power dissipation. Tag reduction is one of them. This paper extends the tag reduction technique on a single-core processor to a multi-core processor and investigates the potential of energy saving for multi-core processors. We formulate our approach as an equivalent problem which is to find an assignment of the whole instruction pages in the physical memory to a set of cores such that the tag-reduction conflicts for each core can be mostly avoided or reduced. We then propose three algorithms using different heuristics for this assignment problem. We provide convincing experimental results by collecting experimental data from a real operating system instead of the traditional way using a processor simulator that cannot simulate operating system functions and the full memory hierarchy. Experimental results show that our proposed algorithms can save total energy up to 83.93% on an 8-core processor and 76.16% on a 4-core processor in average compared to the one that the tag-reduction is not used for. They also significantly outperform the tag reduction based algorithm on a single-core processor.

“…The organization of the tag hardware in a cache is illustrated in Fig.2 [5] . The tag is an array which includes several entries.…”

Section: Energy Saving By Tag Reductionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Energy Efficiency of a Multi-Core Processor by Tag Reduction

J. Comput. Sci. Technol.

Ota

et al. 2011

“…The tag reduction technique [14] [15] [16] [17] is another way to save energy consumed by the cache system and the Table Lookaside Buffer (TLB) in a processor. It has received more attention in the literature because it can save energy of caches significantly.…”

Section: Introductionmentioning

confidence: 99%

“…It has received more attention in the literature because it can save energy of caches significantly. In previous research works, tag reduction is applied to the general or customizable embedded processor [14] [16], to the TLB [15], as well as to the processor using heterogeneously tagged caches [20]. These research works all concentrate on the tag reduction for the single-core processor.…”

Section: Introductionmentioning

confidence: 99%

An Improved Approach to Tag Reduction on Low Power CMP with Trade-Off of Energy and Performance

2009 Fourth International Conference on Frontier of Computer Science and Technology

Jin

et al. 2009

Energy consumption and performance are always major considerations in microprocessor optimization. However, mostly, saving energy causes performance decrement. Based on the previous energy saving research on tag reduction for low power Chip Multiprocessor (CMP), we proposed an improved approach to balance energy and performance by introducing an affiliation degree. To our best knowledge, this is the first work that analyzes the energy and performance of tag reduction on CMP. We also formulate the trade-off of energy and performance to an equivalent problem which is to find out an appropriate affiliation degree to get the benefit with tradeoff of energy and performance most. In the experiment, we apply our approach to a 16-core CMP with help of simulation. The experiment results show that when affiliation degree is 12, the energy saving and performance cost of tag reduction on CMP can be balanced best.

The Core Degree Based Tag Reduction on Chip Multiprocessor to Balance Energy Saving and Performance Overhead

Lecture Notes in Computer Science

Jin

et al. 2010

International audienceTag reduction is an approach to save energy of the cache system in a processor. Our previous work described that it can save more energy on a Chip Multiprocessor (CMP) than on a single-core processor. In this paper, we further investigate the problem on balancing energy saving and performance overhead when tag reduction is used for the low power Chip Multiprocessor (CMP). We first introduce the core degree concept which is defined as the number of cores that tag reduction can use for each thread. We then propose a core degree based tag approach that is to optimize the core degree such that the best balance of energy and performance can be achieved. In particular, as the basis for such optimization, the theoretical upper bounds of the energy savings and performance overhead are decided as function of the core degree. In our experiments, we use a 16-core CMP for example. In order to obtain the energy consumption and performance overhead with various core degrees, we construct an experimental environment, which is based on the Linux operating system. With the experimental environment, benchmarks of SPEC CPU2006 are used to evaluate our core degree based tag reduction. Finally, the experimental results show that the most desired balance of energy saving and performance overhead is achieved when core degree is set to 6