Dynamic strength scaling for delay fault propagation in nanometer technologies

Javaheri, Reza; Sedaghat, Reza

doi:10.1109/csicc.2009.5349362

Cited by 5 publications

(4 citation statements)

References 6 publications

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“…Figure 20 shows a functional representation of a NOT gate. The initial idea is taken from previous publication [57].…”

Section: Soft-error Detection Coding Modelmentioning

confidence: 99%

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

Javaheri¹

2023

Preprint

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Soft-errors (SEs) and delay faults (DFs) frequently occur in modern high-density, high-speed, low-power VLSI circuits. Therefore, SE hardened design and DF testing are essential. This thesis introduces two novel methods for soft-error detection and delay fault propagation in nanometre technology. A new idea is proposed to propagate those delay faults that are not causing logic failure at the site of the defect, but the delay makes the circuit more prone to soft-errors that manifest the effect of delay faults. This approach propagates the fault from the fault location by mapping a nine-valued voltage model on top of a five-valued voltage model to convert delay faults to static faults. This original idea reduces the complexity of delay fault propagation. This thesis introduces an original approach toward soft-error detection based on the strength violation in the circuit. This research shows that transient pulses of less than threshold voltage will cause soft-errors without altering the logic value at the strike location. This method will increase the Soft-Error Rates (SER) for all existing methods if strength-based Soft-Error detection will be considered. The offered approach uses a novel coding system that carries both logic and strength which applies to certain logic functions that are sensitive to strength variations. A wide range of soft-errors are the result of strength violation in switch-level that have never been investigated before.

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“…Figure 20 shows a functional representation of a NOT gate. The initial idea is taken from previous publication [57].…”

Section: Soft-error Detection Coding Modelmentioning

confidence: 99%

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

Javaheri¹

2023

Preprint

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“…Table 1 [14] shows how the logic levels and strength levels are structured and coded. There are 3 logic levels 0, 1, U, called respectively logic 0, logic 1, and unknown.…”

Section: Verilog Strength and Logic Levelsmentioning

confidence: 99%

“…Switchlevel strength-based models using Verilog logic and strength levels were previously used in different works such as [11] where static faults are injected at gate of a switch. Similar switchlevel models are used to study the delay introduced by resistive faults [14]. These switch-level models were used for soft error detection for the first time in the cited publication [15].…”

Section: Verilog Strength and Logic Levelsmentioning

confidence: 99%

Optimized switch-level soft error detection based on advanced switch-level models

Chikhe¹

2021

Preprint

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Due to the reduction of transistor size, modern circuits are becoming more sensitive to soft errors. The development of new techniques and algorithms targeting soft error detection are important as they allow designers to evaluate the weaknesses of the circuits at an early stage of the design. The project presents an optimized implementation of soft error detection simulator targeting combinational circuits. The developed simulator uses advanced switch level models allowing the injection of soft errors caused by single event-transient pulses with magnitudes lesser than the logic threshold. The ISCAS'85 benchmark circuits are used for the simulations. The transients can be injected at drain, gate, or inputs of logic gate. This gives clear indication of the importance of transient injection location on the fault coverage. Furthermore, an algorithm is designed and implemented in this work to increase the performance of the simulator. This optimized version of the simulator achieved an average speed-up of 310 compared to the non-algorithm based version of the simulator.

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“…This makes these advanced switch-level models more realistic and closer to actual transistor behavior. The initial idea has been taken from "to be published" [9] where similar switch-models were used to study the delays introduced by resistive-faults. Currently used soft error modeling methods are based on the assumption that an SET may propagate to the next stage only if the voltage generated by particle strike at a node is more than VDD/2, i.e., if the voltage change at node crosses the logical threshold [10].…”

Section: Introductionmentioning

confidence: 99%

Soft error injection using advanced switch-level models for combinational logic in nanometer technologies

Kalkat

Sedaghat

Chikhe

et al. 2009

2009 International Conference on Microelectronics - ICM

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Due to technology scaling, modern digital systems are becoming more prone to single-event transients (SETs) caused by radiation strikes in CMOS logic devices. This has led to the need for better soft error detection methods in order to increase the reliability of logic circuits in nanometer technologies. Present day soft error detection techniques assume that soft errors occur due to voltage pulses which change the logic state of a transistor node. A novel soft error detection concept is used, assuming that voltage fluctuations smaller than logic threshold can eventually result in soft errors. Advanced switch-level models were designed which mimic important characteristics of transistor-level circuits like bidirectional signal flow, driving strength variations and node capacitances and use verilog driving strengths to model different voltage values. The resulting switch-level models eliminate the complexity associated with state-of-art transistor level simulators while achieving desired amount of accuracy and faster simulation. The aim of this paper is to interpret various parameters used in these strength-based switch models in order to find an efficient way of injecting transients into complex logic circuits. The approach has been evaluated experimentally by creating a simulation environment which allows transient injection at internal nodes of switch-level circuits and injecting a wide range of input test vectors to ISCAS'85 benchmarks. The simulation results show that transient injection at drains of switch-level circuits gives better results in terms of accuracy and prevents over-estimation of soft error rate calculations as compared to injection at gates of transistors.Index Terms-Soft error injection, advanced switch-level models, strength scaling, combinational logic.

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Dynamic strength scaling for delay fault propagation in nanometer technologies

Cited by 5 publications

References 6 publications

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

Fault Detection for ASIC Design Reliability on Resistive Delay Faults and Strength-Based Soft-Errors

Optimized switch-level soft error detection based on advanced switch-level models

Soft error injection using advanced switch-level models for combinational logic in nanometer technologies

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