Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications

Abstract

Near-threshold-voltage (NTV) circuit is to set the operating voltage near the threshold voltage of CMOS transistors to pursue the maximum energy efficiency. However, the characteristics for each logic family are quite different under NTV while comparing to its operation under normal supply voltage. In this paper, we proposed a new dynamic-static hybrid near threshold voltage adder design. The proposed keeper design can suppress the leakage current and avoid signal contention in the dynamic CMOS circuit, which lets the dynamic CMOS logic family can be adapted to NTV environment with excellent speed characteristics and higher energy efficiency. The proposed low leakage dynamic-static hybrid NTV 32-bits adder design can achieve the maximum energy efficiency with 161.7% enhancement as compared to the mirror adder under NTV with 0.3 V.

A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs

“…Near-threshold computing is a promising technique to achieve high energy efficiency by scaling the supply voltage [1]. However, a serious challenge is the significant effect of process variations, voltage disturbances, temperature fluctuations (PVT) on the circuit delay [2].…”