Dynamic SMP Clusters with Communication on the Fly in NoC Technology for Very Fine Grain Computations

Task Scheduling for SoC-Based Dynamic SMP Clusters with Communication on the Fly

“…We have assumed the following variable parameters: the input degree of graph nodes (1)(2)(3)(4), the weight of communication edges (data volume: 25, 50, 100), the system structure (1 to 4 SoC modules up to 16 processors in total). A SoC Algorithm 2 Second phase of the scheduling algorithm 1: {Input: extended macro dataflow graph G} 2: Remove from G the representation of communication between computation nodes mapped to the same processor -it will be done via processor's data cache.…”

“…Dynamic SMP clusters can be internally configured at program run-time to match computational and communication requirements of application programs. Following this, such systems show features of inter-cluster dynamic processor switching and inter-processor data transfers on the fly [2,3]. Dynamic SMP clusters are created inside SoC modules around busses, which connect processors with data memory banks.…”

“…It converts standard data transmissions through memory and/or some global network, into transfers performed directly into data caches. The efficiency of the assumed architecture for typical numerical computations has been demonstrated by numerous simulation experiments [3,4]. The experiments have shown that the architecture is specially advantageous for synchronous computations performed with fine grain parallelism on regular data and for parallel numerical computations with high degree of parallel data sharing.…”

“…This analysis is done by a scheduling algorithm acting on special graph representation of programs [3,4], which expands standard macro data flow graphs by representation of memory to cache data reads, cache to memory data writes, processor switching, synchronization and data transfers on the fly.…”

Fast Matrix Multiplication in Dynamic SMP Clusters with Communication on the Fly in Systems on Chip Technology

“…Processors perform multiple parallel reads of data to data caches take place while one processor writes data from its cache to the cluster memory (reads on the fly, similar to cache injection [4]). Reads on the fly combined with dynamic switching of processors with data cache contents between SMP clusters are called "communication on the fly" [5][6][7][8][9] Processor data caches show multiple access features, which increases efficiency of data cache transactions. Data cache receive/send operations from/to many memory modules are done at the same time.…”