2019
DOI: 10.1016/j.jpdc.2017.09.013
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Dynamic self-reconfiguration of a MIPS-based soft-core processor architecture

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“…The soft-core processor can also be designed for a chosen standard instruction set architecture, such as RISC (Reduced Instruction Set Computer), on a QPU. This is conceptually similar to a soft-core processor designed on a field-programmable gate array (FGPA), [49][50][51][52][53] but there are significant technical differences between the classical and quantum based versions.…”
Section: Conclusion and Discussionmentioning
confidence: 99%
“…The soft-core processor can also be designed for a chosen standard instruction set architecture, such as RISC (Reduced Instruction Set Computer), on a QPU. This is conceptually similar to a soft-core processor designed on a field-programmable gate array (FGPA), [49][50][51][52][53] but there are significant technical differences between the classical and quantum based versions.…”
Section: Conclusion and Discussionmentioning
confidence: 99%