Dynamic reconfiguration to support concurrent applications

Jean, Jack; Tomko, Karen; Yavagal, V.; Shah, J.; Cook, Robert P.

doi:10.1109/12.773796

Cited by 43 publications

(7 citation statements)

References 10 publications

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“…A prominent example is placement and scheduling of hardware tasks, which has been studied under a variety of task and resource models as well as optimization objectives. Examples can be found in Jean et al [1999], Bazargan et al [2000], Teich et al [2000], Steiger et al [2004], Danne and Platzner [2006], Danne et al [2007], and Pellizzoni and • 8:5 Caccamo [2007]. Many efficient scheduling techniques, especially for real-time systems, rely on task preemption.…”

Section: Related Workmentioning

confidence: 97%

ReconOS

Lübbers

Platzner

2009

ACM Trans. Embed. Comput. Syst.

123

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Rising logic densities together with the inclusion of dedicated processor cores push reconfigurable devices from being applied for glue logic and prototyping towards implementing complete reconfigurable systems-on-chip. The mix of fast CPU cores and fine-grained reconfigurable logic allows to map both sequential, control-dominated code and highly parallel data-centric computations onto one platform. However, traditional design techniques that view specialized hardware circuits as passive coprocessors are ill-suited for programming these reconfigurable computers. In particular, the programming models for software-running on an embedded operating system-and digital hardware-synthesized to an FPGA-lack commonalities, which hinders design space exploration and severely impairs the potential for code reuse.In this article, we present ReconOS, an execution environment based on existing embedded operating systems that extends the multithreaded programming model established in the software domain to reconfigurable hardware. Using threads and common synchronization and communication services as an abstraction layer, ReconOS allows for the creation of portable and flexible multithreaded applications targeting CPU/FPGA systems. This article discusses the ReconOS programming model and its execution environment, presents implementations based on modern platform FPGAs and the operating systems eCos and Linux, evaluates time and area overheads of the proposed mechanisms and, finally, demonstrates the feasibility of the multithreading design approach on several case studies.

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Section: Related Workmentioning

confidence: 97%

ReconOS

Lübbers

Platzner

2009

ACM Trans. Embed. Comput. Syst.

123

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“…In this case the problem is much similar to the traditional packing problem [6,7]. An early study in online scenario is discussed by Jean et al [8]. They presented a resource manager that schedules tasks online to a farm of non-partially reconfigurable FPGAs.…”

Section: Related Workmentioning

confidence: 99%

Improving utilization of reconfigurable resources using two-dimensional compaction

2007

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Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affecting the rest of the chip. This allows placement of tasks at run time on the reconfigurable chip. Area management is a very important issue which highly affect the utilization of the chip and hence the performance.This paper focuses on a major aspect of moving running tasks to free space for new incoming tasks (compaction). We study the effect of compacting running tasks to free more contiguous space on the system performance. First, we introduce a straightforward compaction strategy called Blind compaction. We use its performance as a reference to measure the performance of other compaction algorithms. Then we propose a two-dimensional compaction algorithm called one-corner compaction. This algorithm runs with respect to one chip corner. We further extend this algorithm to the four corners of the chip and introduce the four-corners compaction algorithm. Finally, we compare the performance of these algorithms with some existing compaction strategies: ). The simulation results show improvement in average task allocation time when using the four-corners compaction algorithm by 15% and in chip utilization by 16% over the Blind compaction. These results outperform the existing strategies.

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“…[5,10]) and (2) fast scenario switching for industrial automation and telecommunication systems (cp. [1,6,9,19]). …”

Section: Introductionmentioning

confidence: 99%