Dynamic reconfiguration to support concurrent applications

Jean, Jack; Tomko, Karen; Yavagal, V.; Cook, Robert P.; Shah, J.

doi:10.1109/fpga.1998.707926

Cited by 13 publications

(6 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These threads or processes may each have their own sets of configurations that are to be mapped to the reconfigurable hardware. Issues such as the correct use of memory protection and virtual memory must be considered during memory accesses by the reconfigurable hardware [Chien and Byun 1999;Jacob and Chow 1999;Jean et al 1999]. Another problem can occur when one thread or process configures the hardware, which is then reconfigured by a different thread or process.…”

Section: Potential Problems With Rtrmentioning

confidence: 99%

Reconfigurable computing

Compton¹,

2002

View full text Add to dashboard Cite

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.

show abstract

Section: Potential Problems With Rtrmentioning

confidence: 99%

Reconfigurable computing

Compton¹,

2002

View full text Add to dashboard Cite

show abstract

“…[4] deals with the support of concurrent applications in a multi-FPGA system by reconfiguring entire FPGAs. Storing the state information of a hardware task during interruption is discussed in [5].…”

Section: Related Workmentioning

confidence: 99%

A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors

Tuan

Amano

2008

IEICE Transactions on Information and Systems

View full text Add to dashboard Cite

SUMMARY Task preemption is a critical mechanism for building an effective multi-tasking environment on dynamically reconfigurable processors. When a task is preempted, its necessary state information must be correctly preserved in order for the task to be resumed later. Not only do coarse-grained Dynamically Reconfigurable Processing Array (DRPAs) devices have different architectures using a variety of development tools, but the great amount of state data of hardware tasks executing on such devices are usually distributed on many different storage elements. To address these difficulties, this paper aims at studying a general method for capturing the state data of hardware tasks targeting coarse-grained DRPAs. Based on resource usage, algorithms for identifying preemption points and inserting preemption states subject to user-specified preemption latency are proposed. Moreover, a modification to automatically incorporate proposed steps into the system design flow is also discussed. The performance degradation caused by additional preemption states is minimized by allowing preemption only at predefined points where demanded resources are small. The evaluation result using a model based on NEC Electronics' DRP-1 shows that the proposed method can produce preemption points satisfying a given preemption latency with reasonable hardware overhead (from 6% to 15%). key words: dynamically reconfigurable processor, preemption algorithm, preemption latency, hardware overhead

show abstract

“…Thus, it is difficult to sufficiently explore data parallelism inherent in application algorithms. [18] employs an FPGA resource manager to allocate and deallocate FPGA resources for concurrent applications. [13] proposes a three-step approach to map generalized template matching applications onto reconfigurable computers.…”

Section: Introductionmentioning

confidence: 99%

“…[13] proposes a three-step approach to map generalized template matching applications onto reconfigurable computers. [13] [18] implement their designs as software running on the host to specifically explore data parallelism in applications.…”

Section: Introductionmentioning

confidence: 99%

A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers

Ziavras

2006

IEICE Transactions on Information and Systems

View full text Add to dashboard Cite

FPGAs (Field-Programmable Gate Arrays) have been widely used as coprocessors to boost the performance of data-intensive applications [1][2]. However, there are several challenges to further boost FPGA performance: the communication overhead between the host workstation and the FP-GAs can be substantial; large-scale applications cannot fit in a single FPGA because of its limited capacity; mapping an application algorithm to FPGAs still remains a daunting job in configurable system design. To circumvent these problems, we propose in this paper the FPGA-based Hierarchical-SIMD (H-SIMD) machine with its codesign of the Pyramidal Instruction Set Architecture (PISA). PISA comprises high-level instructions implemented as FPGA functions of coarse-grain SIMD (Single-Instruction, Multiple-Data) tasks to facilitate ease of program development, code portability across different H-SIMD implementations and high performance. We assume a multi-FPGA board where each FPGA is configured as a separate SIMD machine. Multiple FPGA chips can work in unison at a higher SIMD level, if needed, controlled by the host. Additionally, by using a memory switching scheme and the high-level PISA to partition applications into coarse-grain tasks, host-FPGA communication overheads can be hidden. We enlist the two-dimensional Fast Fourier Transform (2D FFT) to test the effectiveness of H-SIMD. The test results show sustained high performance for this problem. The H-SIMD machine even outperforms a Xeon processor for this problem.

show abstract

Dynamic reconfiguration to support concurrent applications

Cited by 13 publications

References 10 publications

Reconfigurable computing

Reconfigurable computing

A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors

A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers

Contact Info

Product

Resources

About