Dynamic reconfiguration of streaming graphs on a heterogeneous multiprocessor architecture

Rutten, Martijn J.; Pol, Evert-Jan D.; Eijndhoven, J. van; Walters, K.H.G.; Essink, G.

doi:10.1117/12.586112

Cited by 18 publications

(17 citation statements)

References 7 publications

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“…In aelite, just as AEthereal, the bounds are based on contention-free routing, and thus on the ability to bound the time required for one flit cycle. In this work, we assume that the entire NoC has same nominal frequency 1 . The latency and throughput thus follows directly from the waiting time in the NI (plus the time required to traverse the path), and the fraction of slots reserved, respectively.…”

Section: Resultsmentioning

confidence: 99%

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Aelite: A flit-synchronous Network on Chip with composable and predictable services

Hansson

Subburaman

Goossens

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-To accommodate the growing number of applications integrated on a single chip, Networks on Chip (NoC) must offer scalability not only on the architectural, but also on the physical and functional level. In addition, real-time applications require Guaranteed Services (GS), with latency and throughput bounds. Traditionally, NoC architectures only deliver scalability on two of the aforementioned three levels, or do not offer GS.In this paper we present the composable and predictable aelite NoC architecture, that offers only GS, based on flit-synchronous Time Division Multiplexing (TDM). In contrast to other TDMbased NoCs, scalability on the physical level is achieved by using mesochronous or asynchronous links. Functional scalability is accomplished by completely isolating applications, and by having a router architecture that does not limit the number of service levels or connections. We demonstrate how aelite delivers the requested service to hundreds of simultaneous connections, and does so with 5 times less area compared to a state-of-the-art NoC.

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Section: Resultsmentioning

confidence: 99%

“…Systems on Chip (SoC) grow in complexity with an increasing number of independent applications on a single chip [1]. The applications are realised by hardware and software Intellectual Property (IP), e.g.…”

Section: Introductionmentioning

confidence: 99%

Aelite: A flit-synchronous Network on Chip with composable and predictable services

Hansson

Subburaman

Goossens

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…These heterogeneous highcomplexity chips are programmable and integrate a rich set of applications [5,20], e.g. PDA phones with mp3 players, cameras, radios and gaming.…”

Section: Introductionmentioning

confidence: 99%

Undisrupted Quality-of-Service during Reconfiguration of Multiple Applications in Networks on Chip

Hansson¹,

Coenen²,

Goossens³

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip (SoC) communication infrastructure. Due to convergence, a growing number of applications are integrated on the same chip. When combined, these applications result in use-cases with different communication requirements. The NoC is configured per use-case and traditionally all running applications are disrupted during use-case transitions, even those continuing operation.In this paper we present a model that enables partial reconfiguration of NoCs and a mapping algorithm that uses the model to map multiple applications onto a NoC with undisrupted Quality-of-Service during reconfiguration. The performance of the methodology is verified by comparison with existing solutions for several SoC designs. We apply the algorithm to a mobile phone SoC with telecom, multimedia and gaming applications, reducing NoC area by more than 17% and power consumption by 50% compared to a state-of-the-art approach.

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“…Systems on Chip (SoC) grow in complexity with an increasing number of independent applications on a single chip [35]. The applications are realised by hardware and Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

Section: Introductionmentioning

confidence: 99%

An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

Hansson

Goossens

2009

Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication paradigms, programming models, and interface protocols that the on-chip interconnect must accommodate.Traditionally, on-chip buses offer distributed shared memory communication with established memory-consistency models, but are tightly coupled to a specific interface protocol. On-chip networks, on the other hand, offer layering and interface abstraction, but are centred around point-topoint streaming communication, and do not address issues at the higher layers in the protocol stack, such as memoryconsistency models and message-dependent deadlock.In this work we introduce an on-chip interconnect and protocol stack that combines streaming and distributed shared memory communication. The proposed interconnect offers an established memory-consistency model and does not restrict any higher-level protocol dependencies. We present the protocol stack and the architectural blocks and quantify the cost, both on the block level and for a complete SoC. For a multi-processor multi-application SoC with multiple communication paradigms and programming models, our proposed interconnect occupies only 4% of the chip area.

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Dynamic reconfiguration of streaming graphs on a heterogeneous multiprocessor architecture

Cited by 18 publications

References 7 publications

Aelite: A flit-synchronous Network on Chip with composable and predictable services

Aelite: A flit-synchronous Network on Chip with composable and predictable services

Undisrupted Quality-of-Service during Reconfiguration of Multiple Applications in Networks on Chip

An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

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