Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach

Abstract

Power management of NoC-based many-core systems with runtime application mapping becomes more challenging in the dark silicon era. It necessitates a multi-objective control approach to consider an upper limit on total power consumption, dynamic behaviour of workloads, processing elements utilization, per-core power consumption, and load on networkon-chip. In this paper, we propose a multi-objective dynamic power management method that simultaneously considers all of these parameters. Fine-grained voltage and frequency scaling, including near-threshold operation, and per-core power gating are utilized to optimize the performance. In addition, a disturbance rejecter is designed that proactively scales down activity in running applications when a new application commences execution, to prevent sharp power budget violations. Simulations of dynamic workloads and mixed time-critical application profiles show that our method is effective in honoring the power budget while considerably boosting the system throughput and reducing power budget violation, compared to the state-of-the-art power management policies.

Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications

“…Power capping techniques are used to restrict power consumption of the chip to a fixed and safer limit, beyond which thermal violations may occur [4]. Dynamic power capping and management techniques are triggered in an observe-decide-act loop for power actuation and dark silicon mitigation [5]. Typically, these techniques monitor instantaneous power consumption and temperature accumulation, decide on power actuation, and act on the decisions through power knobs.…”

“…Application mapping i.e., spatial alignment of active cores for improving power budget and thus power capping limit is proposed in [17] and [18]. A multi-objective power capping approach is presented in [5], [19] which uses combination of DVFS and Per-core Power Gating (PCPG) based on network and workload characteristics. Chen et.…”

“…Dynamic workload characteristics contribute to power violations, forcing actuation of power knobs. We simulate the application for 4 different power knobs viz., DVFS, PG, DVFS+PG (referred as MOC) [5], and DVFS+PCPG+APPX, using the experimental platform, detailed in Section VII. The APPX knob has k levels of approximation, where k is a parametrizable entity.…”

“…In case of using DVFS and PG knobs [13], per-application run-time increases forcing incoming applications to wait longer, resulting in high service time. The combination of DVFS and PG has relatively better service time using the power management algorithm, as in [5], [19]. With the APPX knob in combination with DVFS and PG, the service time is the lowest, indicating high performance and energy gain within the given power budget.…”

Network on Chip Router with Power Management Unit for Improved Network Fabric Power Efficiency

“…The majority of DVFS methods focuses on the processor perspective and the communication is not considered. However, there are first developments to extend these methods also to the network layer [2], [3], [4].…”