Dynamic performances of GaN-HEMT on Si in cascode configuration

Hirose, Takahisa; Imai, Masamitsu; Joshin, K.; Watanabe, Keiji; Ogino, Tsutomu; Miyazaki, Y.; Shono, K.; Hosoda, Toru; Asai, Yasufumi

doi:10.1109/apec.2014.6803306

Cited by 28 publications

(10 citation statements)

References 13 publications

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“…• Cascode d-mode HEMT (normally-off) [67]- [69]; the cascode configuration allows to turn a d-mode HEMT into a normally-off device with the simple addition of a low voltage Si MOSFET, connected in the same way as in the cascode SiC JFET structure. This approach allows to combine the superior conduction/switching performance of the d-mode HEMT with the driving simplicity and robustness of a Si MOSFET (i.e., 0 V/+15 V).…”

Section: Gallium Nitride (Gan) [43]-[49]mentioning

confidence: 99%

New FOM-Based Performance Evaluation of 600/650 V SiC and GaN Semiconductors for Next-Generation EV Drives

2022

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in 1993, and the Ph.D. in Electrical Engineering from Politecnico di Torino, Italy, in 2002. He is a Full Professor of Power Electronics and Electrical Drives in the Energy Department "G. Ferraris" and Chairman of the Power Electronics Innovation Center (PEIC) at Politecnico di Torino, Italy. Dr. Bojoi published more than 200 papers covering electrical drives and power electronics for industrial applications, transportation electrification, power quality, and home appliances. He was involved in many research projects with industry for direct technology transfer aiming at obtaining new products. Dr. Bojoi is the co-recipient of 6 IEEE prize paper awards. Dr. Bojoi is a Co-Editor-In-Chief of the IEEE Transactions on Industrial Electronics.

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Section: Gallium Nitride (Gan) [43]-[49]mentioning

confidence: 99%

New FOM-Based Performance Evaluation of 600/650 V SiC and GaN Semiconductors for Next-Generation EV Drives

2022

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“…However, the normally-on feature of d-mode HEMT is not desirable in most applications. Commercial products have already adopted various cascode approaches to stack a high-voltage GaN HEMT and a low-voltage silicon (Si) MOSFET to make them a normally-off device [1][2][3][4][5]. These commercial devices all integrate the two devices inside the package and are not flexible for the gate drive design.…”

Section: Introductionmentioning

confidence: 99%

Cascode GaN HEMT Gate Driving Analysis

Heumesser,

Lai,

Hsieh

et al. 2023

2023 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)

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The aim of this paper is to analyze the conventional cascode gate driving to understand the switching transition and to provide a design guide for the GaN HEMT and its associated packaging. A double-pulse tester has been designed and fabricated with minimum parasitic inductance to avoid unnecessary parasitic ringing. The switching behaviors in both turn-on and -off are analyzed through topological study and explained through SPICE simulation. Two different cascode devices were tested to show the impact of threshold voltage and low-voltage Si MOSFET selection.

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“…It is necessary to consider the electrical parameter variations of the GaN devices at high ambient temperatures when modelling the device behaviours and designing power electronics systems, but comprehensive high temperature information of the commercial GaN devices is hard to be acquired from the datasheet released by the companies or from the articles [7][8][9][10]. For Cascode HEMTs, most of the electrical parameters are determined by the performances of internally integrated Si-based metal-oxidesemiconductor field effect transistor (MOSFET), the physics-based mechanisms behind the behaviours of the whole device at high temperatures can be understood based on the MOSFET, which are relatively mature.…”

Section: Introductionmentioning

confidence: 99%

High‐temperature electrical performances and physics‐based analysis of p‐GaN HEMT device

Liu

Tian

et al. 2020

IET Power Electronics

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High-temperature electrical performances of enhancement-mode (E-mode) high electron mobility transistor with ptype Gallium Nitride (GaN) gate cap are evaluated here. The physics-based mechanisms behind the behaviours are also analysed by the simulations and analytical models. For static electrical performances, the changes of GaN bandgap and the interface states or traps are considered to be influential factors for the little variations of threshold voltage (V T). Meanwhile, the on-state resistance increases and trans-conductance decreases at high temperatures due to the reduction in electron mobility (µ eff). As for blocking characteristic, high temperature-induced increase of leakage current may result from multi-reasons, such as the increase of intrinsic carrier concentration and lowering of trap barrier. In addition, a segmental method is presented to understand the gate leakage current at high temperatures. For capacitance characteristics, the increase of channel resistance makes the measured gate capacitance lower than the intrinsic value. For dynamic electrical performances, the high temperature-induced decrease of µ eff leads to the increase of plateau voltage, bringing the decreases of total switching time and total switching energy loss, which are quite different from those of the devices with traditional metal-oxide-semiconductor structures.

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Dynamic performances of GaN-HEMT on Si in cascode configuration

Cited by 28 publications

References 13 publications

New FOM-Based Performance Evaluation of 600/650 V SiC and GaN Semiconductors for Next-Generation EV Drives

New FOM-Based Performance Evaluation of 600/650 V SiC and GaN Semiconductors for Next-Generation EV Drives

Cascode GaN HEMT Gate Driving Analysis

High‐temperature electrical performances and physics‐based analysis of p‐GaN HEMT device

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